Analog Implementation Research Articles

Geometry modifications of circular saw blades to reduce aeroacoustic noise emissions

In the manufacturing industries, noise is one of the most common health hazards at workplaces. In wood machining, for instance, circular sawing processes in particular produce high noise emissions that often exceed the permitted limits. The main source of noise is the rotating circular saw blade, whose aeroacoustic behavior is influenced by air turbulence on the tool contour. So far, no numerical approach to study and optimize the aeroacoustic noise emissions from circular saw blades has been investigated. This paper addresses this deficit and presents a methodology for modeling the flow-induced sound generation on rotating circular saw blades based on computational fluid dynamics (CFD) simulations. With the implementation of the acoustic analogy according to Ffowcs-Williams/Hawkings, the sound pressure levels could be calculated with sufficient accuracy. With deviations between 7 and 10%, the influence of the rotational speeds could be plausibly modeled. Based on the validated numerical model, geometry variants with various modifications were investigated regarding their potential for reducing sound pressure levels. Based on a conventional reference geometry, different chip space volumes and various modifications to the tooth rim and tooth shape were investigated and evaluated as part of simulative parameter studies. Sound pressure level reductions in the range of 2.2–10.8 dB were achieved. The results obtained and the systematic approach investigated provide a suitable set of instruments for industrial practice. Digital prototypes can be designed at an early stage in the product development phase of circular saw blades regarding their aeroacoustic properties.

Analog Implementation of a Spiking System for Performing Arithmetic Logic Operations on Mixed‐Signal Neuromorphic Processors

In recent years, physical limitations in the integration of transistors in computers have forced the search for low‐computational‐power alternatives in hardware design. Although doubts may arise regarding the limit of the relationship between performance and power consumption in computers, these disappear when considering the brain, which is one of the most efficient computing systems. In this way, bioinspired applications try to benefit from the low‐power consumption present in the biological nervous system. Previous work has shown the feasibility of implementing spiking neural networks that operate in a Boolean manner on digital platforms, such as SpiNNaker, using basic logic gates and a spiking memory, which suggests the potential for constructing a low‐power consumption spiking computer. This work takes a first step in the implementation of a spiking central processing unit by developing an arithmetic logic unit, which is an essential block for instruction execution, demonstrating its correct operation on Dynap‐SE1. The results confirm the feasibility of using this Boolean approach on this platform, despite certain limitations in the number of inputs and operating frequencies of the blocks, and pave the way for the construction of a spiking computer.

Characterizing Matrix-Product States and Projected Entangled-Pair States Preparable via Measurement and Feedback

Preparing long-range entangled states poses significant challenges for near-term quantum devices. It is known that measurement and feedback (MF) can aid this task by allowing the preparation of certain paradigmatic long-range entangled states with only constant circuit depth. Here, we systematically explore the structure of states that can be prepared using constant-depth local circuits and a single MF round. Using the framework of tensor networks, the preparability under MF translates to tensor symmetries. We detail the structure of matrix-product states (MPSs) and projected entangled-pair states (PEPSs) that can be prepared using MF, revealing the coexistence of Clifford-like properties and magic. In one dimension, we show that states with Abelian-symmetry-protected topological order are a restricted class of MF-preparable states. In two dimensions, we parametrize a subset of states with Abelian topological order that are MF preparable. Finally, we discuss the analogous implementation of operators via MF, providing a structural theorem that connects to the well-known Clifford teleportation. Published by the American Physical Society 2024

Analog Implementation of a Spiking Neuron with Memristive Synapses for Deep Learning Processing

Analog neuromorphic prototyping is essential for designing and testing spiking neuron models that use memristive devices as synapses. These prototypes can have various circuit configurations, implying different response behaviors that custom silicon designs lack. The prototype’s behavior results can be optimized for a specific foundry node, which can be used to produce a customized on-chip parallel deep neural network. Spiking neurons mimic how the biological neurons in the brain communicate through electrical potentials. Doing so enables more powerful and efficient functionality than traditional artificial neural networks that run on von Neumann computers or graphic processing unit-based platforms. Therefore, on-chip parallel deep neural network technology can accelerate deep learning processing, aiming to exploit the brain’s unique features of asynchronous and event-driven processing by leveraging the neuromorphic hardware’s inherent parallelism and analog computation capabilities. This paper presents the design and implementation of a leaky integrate-and-fire (LIF) neuron prototype implemented with commercially available components on a PCB board. The simulations conducted in LTSpice agree well with the electrical test measurements. The results demonstrate that this design can be used to interconnect many boards to build layers of physical spiking neurons, with spike-timing-dependent plasticity as the primary learning algorithm, contributing to the realization of experiments in the early stage of adopting analog neuromorphic computing.

A Novel A-RoF and VLC-based Full-Duplex FiWi System for B5G Applications

We propose the concept and report the implementation of a Gbps hybrid full-duplex analog radio-over-fiber (A-RoF)/visible light communication (VLC) laser diode (LD)-based system for beyond the fifth generation (B5G) of mobile network applications. Such hybrid optical wireless architecture is composed of a 3-km single-mode fiber fronthaul based on the A-RoF technology, followed by a 1.3 m VLC-LD-based access network. The latter one employs two counter-propagating visible light beams by using dichroic cube filters (DCFs) at the transmitter and receiver side, enabling the full-duplex mode, and avoiding the use of individual optical filters. As a proof of concept, we experimentally demonstrate a successful deployment of 5G New Radio (NR) hybrid full-duplex A-RoF/VLC system. The system performance is evaluated in terms of root mean square error vector magnitude (EVMRMS), in accordance with the 3rd Generation Partnership Project (3GPP) requirements, and as a function of modulation order. The experimental results demonstrate a downlink throughput of 600 Mbit/s and an uplink throughput of 420 Mbit/s, aligning with the digital performance requirements set by 3GPP.

An optoacoustic field-programmable perceptron for recurrent neural networks.

Recurrent neural networks (RNNs) can process contextual information such as time series signals and language. But their tracking of internal states is a limiting factor, motivating research on analog implementations in photonics. While photonic unidirectional feedforward neural networks (NNs) have demonstrated big leaps, bi-directional optical RNNs present a challenge: the need for a short-term memory that (i) programmable and coherently computes optical inputs, (ii) minimizes added noise, and (iii) allows scalability. Here, we experimentally demonstrate an optoacoustic recurrent operator (OREO) which meets (i, ii, iii). OREO contextualizes the information of an optical pulse sequence via acoustic waves. The acoustic waves link different optical pulses, capturing their information and using it to manipulate subsequent operations. OREO's all-optical control on a pulse-by-pulse basis offers simple reconfigurability and is used to implement a recurrent drop-out and pattern recognition of 27 optical pulse patterns. Finally, we introduce OREO as bi-directional perceptron for new classes of optical NNs.

Fully real-time configurable analogue implementation of continuous-time transfer function: Application on fractional controller

This paper proposes a new electronic analog circuit to realize real-time fully configurable continuous-time transfer function. The proposed circuit serves various purposes, including smart controllers, fractional-order controllers, optimal controllers, anti-aliasing filter, and programmable filters. The input signal of the transfer function is continuous and remains continuous throughout the circuit until the output signal is obtained. The proposed approach decomposes the transfer function into elementary first and/or second-order low-pass filters. A new analog first-order low-pass filter circuit is presented, offering advantages over conventional active first-order low-pass filters circuits. These benefits include DC gain and time constant independent of resistor ohmic values, enabling the use of smaller resistors and capacitors for low frequencies, and an expanded frequency working range. Similarly, a new analog circuit for a second-order low-pass filter is proposed, specifically used to obtain complex conjugate poles. The use of digital potentiometers and digital switches controlled by a micro-controller, makes this analog circuit configurable in real-time. As an application, the new circuit is used to realize fractional integrator controller. The circuit gives good similarity between theoretical and experimental measurements.

Comparison of power consumption in pipelined implementations of the BLAKE3 cipher in FPGA devices

This article analyzes the dynamic power losses generated by various hardware implementations of the BLAKE3 hash function. Estimations of the parameters were based on the results of post-route simulations of designs implemented in Xilinx Spartan-7 FPGAs. The algorithm was tested in various hardware organizations: based on a standard iterative architecture with one round instance in the programmable array, various derived versions with pipeline processing were elaborated, which ultimately led to a set of 6 architectural variants of the cipher, from the iterative case (without pipeline) to one with maximum of 6 pipeline stages. Moreover, the results obtained for the iterative architecture were compared with analogous implementations of the BLAKE2 (direct predecessor) and KECCAK (the foundation of the current SHA-3 standard) algorithms. This case study illustrates the differences (or lack thereof) in the power requirements of these three hash functions when they are implemented on an FPGA platform, and illustrate the significant savings that can be achieved by introducing pipeline to the processing of the BLAKE round.

A novel memristive neuron model and its energy characteristics.

The functional neurons are basic building blocks of the nervous system and are responsible for transmitting information between different parts of the body. However, it is less known about the interaction between the neuron and the field. In this work, we propose a novel functional neuron by introducing a flux-controlled memristor into the FitzHugh-Nagumo neuron model, and the field effect is estimated by the memristor. We investigate the dynamics and energy characteristics of the neuron, and the stochastic resonance is also considered by applying the additive Gaussian noise. The intrinsic energy of the neuron is enlarged after introducing the memristor. Moreover, the energy of the periodic oscillation is larger than that of the adjacent chaotic oscillation with the changing of memristor-related parameters, and same results is obtained by varying stimuli-related parameters. In addition, the energy is proved to be another effective method to estimate stochastic resonance and inverse stochastic resonance. Furthermore, the analog implementation is achieved for the physical realization of the neuron. These results shed lights on the understanding of the firing mechanism for neurons detecting electromagnetic field.

Synchronization of Analog-Discrete Chaotic Systems for Wireless Sensor Network Design

The current work is focused on studying the performance of the Pecora–Carroll synchronization technique to achieve synchronization between the analog and discrete chaos oscillators. The importance of this study is supported by the growing applications of chaotic systems for improving the security of data transmission in various communication layers, primarily on the physical layer. The hybrid analog-discrete approach of implementing chaos oscillators opens new possible communication schemes for wireless sensor network (WSN) applications. The analog implementation of chaos oscillators can benefit the simpler sensor node (SN) integration, while the discrete implementation can be used on the gateway. However, the core of such chaos-based communications is synchronizing analog and discrete chaos oscillators. This work studies two key parameters of analog-discrete chaotic synchronization: chaotic synchronization noise immunity and synchronization speed. The noise immunity study demonstrates the quality of synchronization at various noise levels, while the synchronization speed demonstrates how quickly the analog-discrete synchronization is achieved, along with how quickly the two systems diverge when synchronization is no longer present. The two studies use both simulation-based and hardware-based approaches. In the simulation case, the analog oscillator’s circuit is modeled in LTspice XVII, while in the hardware case, the circuit is implemented on the PCB. In both simulation and hardware studies, the discrete model of the oscillator is implemented in MATLAB R2023b. The studies are performed for two pairs of different chaos oscillators to widen the proposed approach application potential: the Vilnius and RC chaos oscillators. The oscillators have been selected due to their simplicity and similar dynamic behavior for model-based and electrical circuit implementation. The proposed approach also allows us to compare the synchronization of different oscillators in the analog-discrete implementation.

Bionic modeling and dynamics analysis of heterogeneous brain regions connected by memristive synaptic crosstalk

The coupling dynamics between different brain regions has long been a gap in the study of neural dynamics. To overcome this bottleneck, the synaptic crosstalk characterized by coupled memristors is creatively connected to different brain regions characterized by two heterogeneous Hopfield neural networks (HNNs), forming a novel bionic memristive synaptic crosstalk coupled-HNN (MSC-HNN) model for the first time. Rigorous boundedness and stability analyses ensure that coupling dynamics are generated within a bounded region. Utilizing innovative dynamics methods, it is revealed that the plasticity of synaptic crosstalk allows MSC-HNN to exhibit homogeneous dynamics properties globally, and the two internal HNNs preserve heterogeneous bifurcation processes and attractors. Interestingly, when the initial conditions undergo slight variations, the multistability phenomenon is simultaneously represented by the coexisting parameter bifurcation and the local basin of attraction, which enhances the diversity of activities in MSC-HNN. Furthermore, these novel dynamics effects are evaluated and validated through quantitative calculations of complexity measures and spectra. Subsequently, the developed analog and digital circuit implementation paradigms confirm the feasibility and practical value of MSC-HNN.

Design and VLSI implementation of SAR Analog to Digital Converter Using Analog Mixed Signal

Design and VLSI implementation of SAR Analog to Digital Converter Using Analog Mixed Signal

Ultra-Low Power Analog Folded Neural Network for Cardiovascular Health Monitoring.

Wearable sensors are increasingly used for continuous health monitoring, but their small size limits battery capacity, affecting user experience and monitoring capabilities. To overcome this, we introduce an ultra-low power analog Folded Neural Network (FNN) for physiological signal processing in a batteryless fashion. Our proposed FNN, by serializing computation, provides several benefits over traditional analog implementations, such as lower space, lower power consumption, and lower peak-to-average power ratio. We evaluate our method extensively using a dataset designed for ECG-based screening and diagnosis. Our analysis considers factors such as thermal noise, spatial requirements, and power consumption. Additionally, we evaluate detection performance, investigating various parameters of the proposed FNN. This evaluation provides insights into the optimal configuration for accurate anomaly detection. We observe a good trade-off for accuracy around 6 layers and a hidden size of 30 and further demonstrate that such architecture could be implemented in a wearable device and executed in a batteryless fashion.

Analog real time tunable and configurable fractional order PID controller realization

Fractional-order controllers are modeled using irrational continuous-time transfer functions. Implementing these controllers in analogue form can be challenging, particularly if their parameters need to be adjusted in real-time. This paper presents an analogue implementation of a fractional PID controller that can be adjusted and configured in real-time. The controller can be configured as PIαDf, PIDβ, PIα, PDβ, Iα, Dβ. The signal within the proposed controller’s circuit stays analog and is not converted into discrete values. A prototype of the controller is tested. The results of the frequency and time domain validations indicated similarity between the theoretical, simulated and experimental measurements.

Digital control of the synchronous modes of the two-rotor vibration set-up

The work is devoted to study of the effectiveness of the algorithm for controlling the synchronization of the rotors of a vibration unit (VU) with the digital implementation of the specified algorithm. A computer study of the dynamics of a two-rotor VU with a digital implementation of the control algorithm for rotor synchronization is carried out in the MATLAB environment. As a result the permissible sampling interval for calculating discrete control values using a zero-order extrapolator circuit was estimated. Also, using modeling, a comparative analysis of the efficiency of synchronization control in digital and analog implementation of the algorithm was carried out. It is shown that with an increase in the specified operating speed of the rotors, determined by the value of the energy H^∗ specified in the algorithm, the permissible value of the sampling interval decreases significantly. Comparison of the VU dynamics with the same values of the parameters of the synchronization control algorithm shows that the time of synchronization and the transient process in both cases are almost the same.

Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip

In this paper, we propose a compact and low-power mixed-signal approach to implementing convolutional operators that are often responsible for most of the chip area and power consumption of Convolutional Neural Network (CNN) processing chips. The convolutional operators consist of several multiply-and-accumulate (MAC) units. MAC units are the primary components that process convolutional layers and fully connected layers of CNN models. Analog implementation of MAC units opens a new paradigm for realizing low-power CNN processing chips, benefiting from less power and area consumption. The proposed mixed-signal convolutional operator comprises low-power binary-weighted current steering digital-to-analog conversion (DAC) circuits and accumulation capacitors. Compared with a conventional binary-weighted DAC, the proposed circuit benefits from optimum accuracy, smaller area, and lower power consumption due to its symmetric design. The proposed convolutional operator takes as input a set of 9-bit digital input feature data and weight parameters of the convolutional filter. It then calculates the convolutional filter’s result and accumulates the resulting voltage on capacitors. In addition, the convolutional operator employs a novel charge-sharing technique to process negative MAC results. We propose an analog max-pooling circuit that instantly selects the maximum input voltage. To demonstrate the performance of the proposed mixed-signal convolutional operator, we implemented a CNN processing chip consisting of 3 analog convolutional operators, with each operator processing a 3 × 3 kernel. This chip contains 27 MAC circuits, an analog max-pooling, and an analog-to-digital conversion (ADC) circuit. The mixed-signal CNN processing chip is implemented using a CMOS 55 nm process, which occupies a silicon area of 0.0559 mm2 and consumes an average power of 540.6 μW. The proposed mixed-signal CNN processing chip offers an area reduction of 84.21% and an energy reduction of 91.85% compared with a conventional digital CNN processing chip. Moreover, another CNN processing chip is implemented with more analog convolutional operators to demonstrate the operation and structure of an example convolutional layer of a CNN model. Therefore, the proposed analog convolutional operator can be adapted in various CNN models as an alternative to digital counterparts.

Dynamics investigation and chaos-based application of a novel no-equilibrium system with coexisting hidden attractors

This work presents a novel three-dimensional system with multiple types of coexisting attractors (including chaotic, periodic, quasi-periodic, and unbound divergent orbit) that are categorized as hidden attractors and investigates its dynamics via the Lyapunov exponent spectrum, phase diagrams, and basins of attraction. The mechanism of the emergence of chaos is explored through numerical simulation. Under some conditions, the periodic orbits embedded in the new system without equilibria are studied using the variational method, and effective symbolic coding with four letters is successfully established to classify all short cycles. The symbols proposed by the method are highly consistent with the calculated results. Furthermore, the analogous circuit implementation is executed to demonstrate the flexibility and validity of the new system that possesses coexisting attractors. Finally, chaos-based applications of the new system, including synchronization, offset boosting control, and image encryption, are presented to show system’s feasibility.

Yet New Extreme Multistable Chaotic System

The upsurge of discovering complex dynamics in simple chaotic systems is spring up in academia. This essay is devoted to investigating extreme multistability in a simple chaotic system. Here, only six terms with one nonlinearity form the mathematical model of this system and brings it infinitely many unstable equilibria. The unstable equilibria make the system possess the ability to yield extreme multistability, including various types of chaotic and periodic attractors. The dynamic behaviors, e.g. extreme multistability and total amplitude control are numerically studied. To verify the proposed system’s physical existence, an analog circuit and implementation utilizing the microcontroller is devised as well, where their outcomes perfectly matched with those of simulations.

Spintronic Hodgkin-Huxley-Analogue Neuron Implemented with a Single Magnetic Tunnel Junction

Spiking neural networks aim to emulate the brain's properties to achieve similar parallelism and high processing power. A caveat of these neural networks is the high computational cost for emulation, while current proposals for analogue implementations are energy inefficient and not scalable. We propose a device based on a single magnetic tunnel junction to perform neuron firing for spiking neural networks without the need for any resetting procedure. We leverage two areas of physics, magnetism and thermal effects, to obtain biorealistic spiking behavior analogous to the Hodgkin-Huxley model of the neuron. The device is also able to emulate the simpler leaky-integrate-and-fire model. Numerical simulations using experimental-based parameters demonstrate firing frequency in the megahertz to gigahertz range under constant input at room temperature. The compactness, scalability, low cost, CMOS compatibility, and power efficiency of magnetic tunnel junctions advocates for their broad use in hardware implementations of spiking neural networks.

Universal Synchronous Rectification Scheme for LLC Resonant Converter Using Primary-Side Inductor Voltage

In recent years, many advanced modulation strategies have been applied in LLC resonant converters, resulting in the increased demand for the synchronous rectification (SR) schemes without modulation strategy limitation. However, the conventional universal SR schemes are mainly on the basis of primary/secondary side current or drain-source voltage of synchronous rectifiers, which are limited by high cost of current transformer (CT) and loss of duty cycle caused by parasitic inductance, respectively. To deal with these problems, this paper proposes a novel SR scheme for LLC resonant converter. Firstly, a SR analysis method on the basis of the idea of power transmission is proposed. It can decouple SR from modulation strategy. Based on this method, this paper proposes a universal SR scheme using primary-side inductor voltage. The scheme is no longer restricted by the modulation strategy of converter. Meanwhile, no CT is required, thereby reducing the cost and conduction loss. Thanks to the large signal sensing-based, this scheme has good noise immunity. Moreover, it eliminates the negative effect of parasitic inductance by integral operation. With these effects, it has high accuracy of SR. Furthermore, an easily-debugged analog implementation is designed, which only needs to adjust one component parameter. Finally, experimental results show that the proposed scheme is compatible with different modulation strategies, and it has higher efficiency than the commercial SR scheme in a wide range of operating conditions.