Analog Front-end IC Research Articles

A Low-power Neural Signal Acquisition Analog Front-end IC for Closed-loop Neural Interfaces

This paper presents an ultra-low-power neural signal recording analog front-end IC (AFE) which is comprised of a low-noise amplifier (LNA) followed by a programmable gain amplifier (PGA). To achieve good overall performance while handling stimulation artifacts in closed-loop neural interface systems, the proposed LNA is designed for moderate gain, low input noise, and, good linearity while the PGA is included for additional gain and tunable bandwidth functions. Implemented using 0.18-㎛ CMOS process, the AFE achieves a measured closed-loop gain of 20 to 40 ㏈ and integrated input referred noise of 3.39 ㎶rms over 1 ㎐ to 6.5 ㎑. The IC consumes 1.49 ㎼ at 1-V supply and the noise efficiency factor is 1.93. For less than 1% total harmonic distortion, the AFE can accommodate up to 60 ㎷pp and 280 ㎷pp of differential and common-mode stimulation artifacts, respectively.

A High Frame Rate Analog Front-End IC With Piezoelectric Micromachined Ultrasound Transducers Using Analog Multi-Line Acquisition for Ultrasound Imaging Systems

This paper proposes a high frame rate analog front-end (AFE) IC combined with a piezoelectric micromachined ultrasonic transducer (PMUT) for ultrasound imaging systems (UISs). The proposed AFE IC, which consists of 8-channel transceivers and a peripheral circuit, employs analog multi-line acquisition (AMLA) based on sub-array beamforming. This AMLA generates multiple scanlines during a scan time by simultaneously and precisely controlling the delay of the AFE IC, thus achieving the high frame rate of the AFE IC. The sensitivities of the PMUT for transmitting and receiving ultrasound waves are simulated to be 67.5 kPa/V and 1.2 mV/kPa, respectively, which are high enough to mitigate the needs of the high-voltage electronics for UISs. The proposed AFE IC was fabricated using a 0.18-μm silicon-on-insulator process and occupies an active area of 2.56 mm × 1.68 mm. The measurement results using the simulated PMUT parameters show that the proposed AFE IC with the AMLA precisely controls its delay up to 1 μs at a clock frequency of 40 MHz. It also acquires more than 9,000 scan/s even at a focal depth of 150 mm, which is at least twice greater than those of prior works, achieving a high frame rate of 93 Hz when 100 scanlines are used for a frame. In addition, a figure-of-merit, which considers the energy consumption per channel/scan and the energy loss, is achieved to be 20 nJ/scan/dB at a focal depth of 150 mm and a center frequency of 3.6 MHz; this is the best result compared to previously reported works. Therefore, the proposed AFE IC is suitable for UISs requiring a high frame rate.

A Sensing Mode Reconfigurable Analog Front-End IC for Capacitive Touch and a-IGZO TFT-Based Active-Matrix Capacitive Fingerprint Sensors

In this paper, we propose a sensing mode reconfigurable analog front-end (AFE) IC for a capacitive touch sensor (CTS) and amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT)-based active-matrix capacitive fingerprint sensor (CFS). The CTS consists of the transmit and receive electrodes for enabling the mutual-capacitance (CM) sensing mode, which can detect the multi-touch. The CFS has the array of a-IGZO TFT and a sensing electrode for enabling the self-capacitance (CS) sensing mode to achieve the high sensitivity. In addition, it can reduce the number of sensing lines by adopting the active-matrix type structure to achieve the low-manufacturing cost. To sense the CTS and CFS, the proposed AFE IC is reconfigured to operate the CM and CS sensing modes, respectively. The proposed AFE IC was fabricated using a $0.13~\mu \text{m}$ CMOS process technology with 20 V high-voltage devices, and demonstrated with a $128\times 72\,\,32$ -inch CTS and a $96\times 96\,\,0.27$ -inch CFS, which represents a pixel resolution of 500 pixel-per-inch. The proposed AFE IC achieves the signal-to-noise ratios of 47.8 dB and 25.0 dB for the CTS and CFS, respectively.

High Input Impedance Low-Noise CMOS Analog Frontend IC for Wearable Electrocardiogram Monitoring

This brief presents a CMOS analog frontend (AFE) IC with high input impedance low input-referred noise, which for wearable electrocardiogram monitoring. The IC has three main parts, pseudo-differential chopper-stabilized instrumentation amplifier, switched capacitor filter, and low-power continuous–time <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${{\Sigma}} {{\Delta }}$ </tex-math></inline-formula> modulator. The pseudo-differential structure with chopper stabilization improves the input impedance, input–referred noise and chip area. Notably, we propose a new type of negative capacitor circuit to further boost the input impedance. Furthermore, the auto-zero technique is applied to the ripple reduction loop for suppressing the second harmonic ripple and maintain operation throughout the loop cycle. A dc servo loop suppresses the electrode dc offset. In <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process, the proposed AFE IC occupies an active area of 0.99 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , consumes 5.8/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$46.6~\mu \text{A}$ </tex-math></inline-formula> from a 1.8 V supply, and achieves an input impedance above 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}{{\Omega }}$ </tex-math></inline-formula> , a CMRR of 102 dB and a PSRR of 72 dB.

A Biomedical Sensor System With Stochastic A/D Conversion and Error Correction by Machine Learning

This paper presents a high-precision biomedical sensor system with a novel analog-frontend (AFE) IC and error correction by machine learning. The AFE IC embeds an analog-to-digital converter (ADC) architecture called successive stochastic approximation ADC. The proposed ADC integrates a stochastic flash ADC (SF-ADC) into a successive approximation register ADC (SAR-ADC) to enhance its resolution. The SF-ADC is also used as a digitally controlled variable threshold comparator to provide error correction of the SAR-ADC. The proposed system also calibrates the ADC error using the machine learning algorithm on an external PC without additional power dissipation at a sensor node. Due to the flexibility of the system, the design complexity of an AFE IC can be relaxed by using these techniques. The target resolution is 18 bits, and the target bandwidth (without digital low-pass filter) is about 5 kHz to deal with several types of biopotential signals. The design is fabricated in a 130-nm CMOS process and operates at 1.2-V supply. The fabricated ADC achieves the SNDR of 88 dB at a sampling frequency of 250 kHz by using the proposed calibration techniques. Due to the high-resolution ADC, the input-referred noise is 2.52 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> with a gain of 28.5 dB.

A Highly Linear, AEC-Q100 Compliant Signal Conditioning IC for Automotive Piezo-Resistive Pressure Sensors

In this paper, the design of a signal conditioning analog front-end (AFE) IC for an automotive piezo-resistive type pressure sensor is presented. To improve the pressure-sensing accuracy and compensate for variations in the pressure sensor and signal conditioning IC, gauge factor calibration, digital automatic offset, and gain calibration are proposed and implemented with low power consumption. By using a high-resolution analog-to-digital converter and digital-to-analog converter, the digital automatic calibration circuit can guarantee linearity of output voltage with respect to pressure to within 0.5%. As the analog signal is converted to a digital signal, accuracy in the AFE IC improves. To improve the reliability in the automotive environment, over-voltage and reverse-voltage protection circuits are integrated with the electrostatic discharge protection circuit. Also, electromagnetic interference is reduced by using the proposed spread spectrum clock generator. The proposed design is implemented using 2P4M 0.35 μm CMOS technology with an active area of 1.94 mm × 1.94 mm. Full output ranges from 0.5 to 4.5 V. The ratiometricity error is within ±0.25% when the supply voltage is changed by ±10%. Current consumption is 4.7 mA from a 5 V supply. The output accuracy is within ±0.5% with respect to the PVT variations.

A 3.9-kHz Frame Rate and 61.0-dB SNR Analog Front-End IC With 6-bit Pressure and Tilt Angle Expressions of Active Stylus Using Multiple-Frequency Driving Method for Capacitive Touch Screen Panels

This paper proposes an analog front-end (AFE) IC using a multiple-frequency driving method (MFDM). The proposed AFE IC achieves a high signal-to-noise ratio (SNR) by using an external noise spectrum and locating the frequencies of the excitation signals in low-noise regions. In addition, it employs the MFDM to increase the frame rate by simultaneously sending excitation signals having multiple frequencies to the touch screen panel (TSP). The proposed AFE IC extracts the coordinates of the finger as well as the coordinates, pressure, and tilt angle of the active stylus with the force gauge and gyro sensor. The proposed AFE IC and active stylus were fabricated in a 0.13- $\mu \text{m}$ standard CMOS process. The measurement results show that the proposed AFE IC achieves a frame rate of 3.9 kHz, and SNRs of 61.0 and 50.1 dB when a finger and active stylus are used, respectively. In addition, the pressure and tilt angle of the active stylus are expressed with 6-bit resolution. A capacitive touch system with the proposed AFE IC is demonstrated with a 65-in $104\times 64$ TSP using ten fingers and the active stylus with the pressure and tilt angle.

A new type battery management system for Li-ion cell packs

Aim: Structured a new type battery management system. Methods: Mainly combined the analog front end IC of ml523x with ml610q488P to compose the core of the BMS. Results: The system performs an intelligent BMS and provides an intelligent battery pack. Conclusion: The system is more inexpensive than any other BMS and performances the same function as well as reliability.

A bidirectional neural interface CMOS analog front-end IC with embedded isolation switch for implantable devices

A bidirectional neural interface analog front-end IC with both stimulation and recording functions is implemented using 0.18-µm standard CMOS process. The proposed IC is comprised of a bipolar biphasic neural stimulator using a transistor-stacked current-mirror driver to achieve good current matching performance in stimulation mode and low-voltage capacitive feedback neural amplifiers for recording mode. In order to save die area, high-voltage isolation switches are embedded within the stimulator core to protect the low-voltage recording circuits from damage. Despite using a low-voltage process, the stimulator is able to deliver up to 1mA current through 10kΩ load using 12.8V supply voltage and the recording amplifier uses 0.8V supply voltage while consuming 1µA of current. The complete IC occupies 0.29mm2 of die area and can be applied for various multi electrode array interface bidirectional neural SoCs in medical implant devices.

Analog front-end measuring biopotential signal with effective offset rejection loop.

This paper presents an analog front-end (AFE) IC design for recording biopotential signals. The AFE employs a capacitively coupled instrumentation amplifier to achieve a low-noise and high-common mode rejection ratio (CMRR) system. A ripple reduction loop is proposed to reduce the ripple generated by the up-modulating chopper. The low frequency noise is attenuated by an input AC coupling capacitor, and is attenuated again by a DC servo loop. The proposed AFE features a differential gain of 71 dB, and a CMRR of 89 dB, at 50 Hz. Furthermore, the proposed AFE can robustly acquire biopotential signals even in the presence of an input offset and ripples.

A 143&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\,\times\,$&lt;/tex&gt; &lt;/formula&gt;81 Mutual-Capacitance Touch-Sensing Analog Front-End With Parallel Drive and Differential Sensing Architecture

This paper presents an analog front-end (AFE) IC for mutual capacitance touch sensing with 224 sensor channels in 0.18 $~\mu\hbox{m}$ CMOS with 3.3 V drive voltage. A 32-in touch sensing system and a 70-in one having 37 dB SNR for 1 mm diameter stylus at 240 Hz reporting rate are realized with the AFE. The AFE adopts a parallel drive method to achieve the large format and the high SNR simultaneously. With the parallel drive method, the measured SNRs of the AFE stay almost constant at a higher level regardless of the number of sensor channels, which was impossible by conventional sequential drive methods. A novel differential sensing scheme which enhances the immunity against the noise from a display device is also realized in the AFE. While the coupled LCD is on and off, the differences between the measured SNRs are less than 2 dB.

A Low-Power CMOS Analog Front-End IC with Adjustable On-Chip Filters for Biosensors

This paper presents a low-power CMOS analog front-end (AFE) IC designed with a selectable on-chip dual AC/DC- coupled paths for bio-sensor applications. The DC-coupled path can be selected to sense a biosignal with useful DC information, and the AC-coupled path can be selected for sensing the AC content of the biosignal by attenuating the unwanted DC component. The AFE IC includes a DC-coupled instrumentation amplifier (INA), two variable-gain 1st-order low pass filters (LPF) with tunable cut-off frequencies, a fixed gain 2nd-order Sallen-Key high-pass filter (HPF) with tunable cut-off frequencies, a buffer and an 8-bit differential successive approximation register (SAR) ADC. The entire AFE channel is designed and fabricated in a proprietary 0.35-μm CMOS technology. Excluding an external buffer needed to properly drive the ADC, the measured AFE IC consumes only 2.37 μA/channel with an input referred noise of ~40 μVrms in [1 Hz, 1 kHz], and successfully displays proper ECG (electrocardiogram) and electrogram (EGM) waveforms for QRS peaks detection. We expect that the low-power dual-path design of this AFE IC can enable it to periodically record both the AC and the DC signals for proper sensing and calibration for various bio-sensing applications.

Development of 16-channels Compact EEG System Using Real-time High-speed Wireless Transmission

For the convenience of people with disability and for normal people, a demand for intelligent interfaces is ever increasing and therefore related studies are actively being conducted. Recently a study is being conducted to develop an interface through face expression, movement of the body and eye movements, and further more active attempts to use electrical signals(brainwave, electrocardiogram, electromyogram) measured from the human body is also actively being progressed. In addition, the development and the usage of mobile devices and smart devices are promoting these research activities even more. The brainwave is measured by electrical activities between nerve cells in the cerebral cortex using scalp electrodes. The brainwave is mainly used for diagnosis and treatment of diseases such as epilepsy, encephalitis, brain tumors and brain damage. As a result, the brainwave measurement methods and analytical methods were developed. Interface using the brainwave will not go through language or body behavior which is the result of the information processed by the brain but will pass directly to the system providing a brain-computer interface (BCI). This is possible because a variety of the brainwave appears depending on the human’s physical and mental state. Using the brainwave with the intelligent brain-computer interface or combining it with mobile devices and smart devices, regardless of space constraints, the brainwave measurement should be possible.[4,7] In this study, in order to measure the brainwave without spatial constraint, 16 channel compact brainwave measurements system using a high-speed wireless communications were designed. It was designed with a 16 channel to classify the various brainwave patterns that appear and for estimating the location of the nerve cells that triggered the brainwave. And in order to transmit the brainwave data within the channel without loss, a high-speed wireless communication must be possible that can enable a high-speed wireless transmission more sufficient than the Bluetooth, therefore, 802.11 compliant Wi-Fi communication methods were used to transfer the data to the PC. In addition, by using an analog front-end IC having a single-chip configuration with real-time digital filters, the miniaturization of the system was implemented and in order to verify the system Eye-blocking was used to observe the changes in the EEG signal.

CMOS Analog Front-End IC for Gas Sensors

An electrochemical sensor readout analog front-end (AFE) IC for recording long term chemical and gas exposure is presented. The AFE readout circuit enables the detection of exhaust fumes in hazardous diesel and gasoline equipment, which helps correlate atmospheric pollutants with severe illnesses. The AFE reads out the output of eight conductometric sensor arrays and eight amperometric sensor arrays. The IC consists of a low noise potentiostat and associated 9 bits current-steering DAC for sensor stimulus, followed by the first order nested chopped ΣΔ ADC. The conductometric sensor uses a current driven approach for extracting resistance change of the sensor depending on gas concentration. The amperometric sensor uses a potentiostat to apply constant voltage for measuring current out of the sensor after a chemical reaction. The core area for the AFE is 2.65x0.95 mm2. The IC is fabricated in 0.18μm CMOS process and achieves 91dB SNR with 1.32mW power consumption per channel from a 1.8 V supply. With digital offset storage and nested chopping, the readout IC achieves 500 μV input referred offset. In order to use the system with AFE as part of a compact badge with battery, the entire gas detection system has been designed in 3D layers with a bio sensor mounted layer, an AFE layer, power management layer, a micro controller layer, and battery.

A CMOS analog front-end IC for portable EEG/ECG monitoring applications

A new digital programmable CMOS analog front-end (AFE) IC for measuring electroencephalograph or electrocardiogram signals in a portable instrumentation design approach is presented. This includes a new high-performance rail-to-rail instrumentation amplifier (IA) dedicated to the low-power AFE IC. The measurement results have shown that the proposed biomedical AFE IC, with a die size of 4.81 mm/sup 2/, achieves a maximum stable ac gain of 10 000 V/V, input-referred noise of 0.86 /spl mu/ V/sub rms/ (0.3 Hz-150 Hz), common-mode rejection ratio of at least 115 dB (0-1 kHz), input-referred dc offset of less than 60 /spl mu/V, input common mode range from -1.5 V to 1.3 V, and current drain of 485 /spl mu/A (excluding the power dissipation of external clock oscillator) at a /spl plusmn/1.5-V supply using a standard 0.5-/spl mu/m CMOS process technology.

A highly integrated analog front-end for 3g

This paper describes a reconfigurable analog front-end (AFE) and audio codec IC supporting the wideband code division multiple access (WCDMA) standard. The chip is fabricated on Intel's 0.18-/spl mu/m (SOC) flash+logic+analog (FLA) process technology using a 0.35-/spl mu/m feature size analog transistor. The transmit path contains a 10-bit segmented rail-to-rail digital-to-analog converter, automatically tunable active RC filter, and programmable gain amplifier (PGA) with self-tuning gain and offset correction circuit. The receive path incorporates a PGA, active RC filter, and an 8-bit analog-to-digital converter with built-in offset correction. The AFE operates at 2.7 V with a current consumption of 55 mA and total active area of 15 mm/sup 2/.

An ADSL-RT full-rate analog front end IC with integrated line driver

An analog front end IC for ADSL systems compliant with ANSI, ITU, and ETSI standards is presented. The IC contains all analog functions on one silicon die, including programmable gain amplifiers, highly linear continuous-time filters, 14-bit DAC and ADC for up to 1.1-MHz signal bandwidth, digitally controlled crystal oscillator, and a line driver capable of delivering +13 dBm to the line. The IC has been fabricated in a mixed-signal 0.6-/spl mu/m DPTM BiCMOS technology with a chip area of 29 mm/sup 2/ and a power consumption of only 800 mW, using 3.3-V supply for all blocks, except 12-V supply for the line driver. The high level of integration together with the low power consumption can be considered a benchmark for full-rate ADSL analog front end ICs.

A CMOS HDSL2 analog front-end

A 5-V 0.5-/spl mu/m CMOS analog front-end (AFE) IC for HDSL2 incorporates transmit digital-to-analog converter (DAC), transmit filters, output buffer, receive AGC, and receive ADC. The AFE consumes 525 mW and provides better than 82-dB signal-to-noise-and-distortion ratio (SNDR) in both transmit and receive paths. It supports variable data rates from 64 kb/s up to 2.32 Mb/s, and enables an HDSL2 system to achieve better than 14 kft of noise-free reach (on 26-gauge wire) at 1.544 Mb/s.

A high-performance analog front-end 14-bit codec for 2.7-V digital cellular phones

A low-voltage, low-power, CMOS-programmable analog front-end IC for 2.7-V digital cellular phone applications is presented. The chip can be configured either as a classical A//spl mu/ law PCM codec or as a 14-bit uniform codec. The main objective of the uniform codec is to achieve a signal-to-noise (S/N) and a signal-to-total-harmonic-distortion (S/THD) ratio for the complete A/D and D/A paths better than 80 dB at full scale. A high-performance speech interface is made of a microphone preamplifier with about 0.5 mV offset and 1.3 /spl mu/V/sub rms/ input-referred noise for the transmit channel, and two power amplifiers capable of driving toads up to 27 /spl Omega/ or 50 nF with 4 V/sub pp/ output voltages and -80 dB of THD in the receive path. A tone generator that can also be used for ringing or DTMF signaling purposes, and a dedicated pulsewidth-modulated (PWM) output for a buzzer complete the chip functions. All programmable functions can be accessed via a standard four-wire control interface. This performance has been achieved from a 2.7-V supply with operative and standby power consumptions of 13 mW and 1.5 /spl mu/W, respectively. The chip area is 10.5 mm/sup 2/ (including scribe line) in a 0.5-/spl mu/m n-well CMOS technology.