Analog Finite Impulse Response Research Articles

Design and analysis of ultra-low power third-harmonic receiver with enhanced conversion gain and out-of-band rejection for IEEE 802.11ba

This paper presents an ultra-low power (ULP) receiver with enhanced conversion gain and high out-of-band rejection for Wi-Fi 802.11ba. The proposed third-harmonic mixer based on 6-phase non-overlap local oscillator (LO) not only minimizes power of the radio frequency (RF) front-end, but also improves out-of-band rejection. In addition, the 8-bit analog finite impulse response (AFIR) low-pass filter is designed in the baseband circuit, which can greatly improve the adjacent channel rejection (ACR) of the receiver with ultra-low power consumption. Meanwhile, the zero-power tunable tapped-capacitor resonator is proposed, which alleviate the resonance frequency offset impact by using switched capacitors for process corners compensation. This 802.11ba receiver is designed in a 65-nm CMOS process occupying an active area of 0.25 mm2. Post-layout simulation results show that, when operating at 2.4 GHz, the receiver achieves an ACR of 93 dB and a voltage gain of 51 dB. It consumes 197 μW DC power from 0.7 V supply voltage.

A 128 Gb/s 7-Tap FIR Filter in 130 nm SiGe BiCMOS for High-Speed Channel Equalization

In this letter, a fully analog differential 7-tap 128 Gb/s finite impulse response (FIR) filter using IHP’s 130 nm SG13G2 SiGe:C BiCMOS process is presented. The design includes microstrip transmission line (TL) delay structures for introducing 3 ps tap delay, which corresponds to a third-bit period at 112 Gb/s. Detailed measurements show that the filter is capable of eye diagram improvements up to 128 Gb/s while consuming 693 mW, demonstrating its suitability for new generation 400 Gb/s communication channels. To the best of the authors’ knowledge, this is the fastest NRZ equalization by a fully analog FIR filter, to be found in the literature.

2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter

High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 × compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal-oxide-semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It consumes 370 μW from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has -7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a -22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

Low-Power Highly Selective Channel Filtering Using a Transconductor–Capacitor Analog FIR

Analog finite-impulse-response (AFIR) filtering is proposed to realize low-power channel selection filters for the Internet-of-Things receivers. High selectivity is achieved using an architecture based on only a single-time-varying- transconductance and integration capacitor. The transconductance is implemented as a digital-to-analog converter and is programmable by an on-chip memory. The AFIR operating principle is shown step by step, including its complete transfer function with aliasing. The filter bandwidth and transfer function are highly programmable through the transconductance coefficients and clock frequency. Moreover, the transconductance programmability allows an almost ideal filter response to be realized by careful analysis and compensation of the parasitic circuit impairments. The filter, manufactured in 22-nm FDSOI, has an active area of 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Its bandwidth can be accurately tuned from 0.06 to 3.4 MHz. The filter consumes 92 μW from a 700-mV supply. This low power consumption is combined with a high selectivity: f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-60dB</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dB</sub> = 3.8. The filter has 31.5-dB gain and 12-nV/√Hz input-referred noise for a 0.43-MHz bandwidth. The OIP3 is 28 dBm, independent of the frequency offset. The output-referred 1-dB-compression point is 3.7 dBm, and the in-band gain compresses by 1 dB for an -3.7-dBm out-of-band input signal while still providing >60 dB of filtering.

A Low-Power, High-Linearity Wideband 3.25 GS/s Fourth-Order Programmable Analog FIR Filter Using Split-CDAC Coefficient Multipliers

This article presents a 3.25 GS/s fourth-order programmable analog finite impulse response (AFIR) filter for flexible discrete time analog signal processing (DT-ASP). For wide application of the proposed AFIR filter, it is designed for full bandwidth utilization up to the Nyquist rate, programmable via the multiplier coefficient set. In this implementation of the FIR function, split-capacitive DACs (split CDACs) are adopted as coefficient multipliers, providing high-linearity over the full frequency range and low power consumption. Individual coefficients are digitally controlled with total 7-bit codes, consisting of 6-bit fractional value, and 1-bit for sign selection. The addition is simply implemented in the current-domain. Noise and effects of the time-interleaved operation are analyzed to understand limitations on the dynamic range. The proposed AFIR filter is implemented in 32-nm SOI CMOS technology; the core area of the circuit is 0.1 mm2. Measurement results demonstrate transfer function configurability over all possible low pass filter (LPF), bandpass filter (BPF), and high pass filter (HPF) linear phase coefficient sets. The AFIR filter achieves > 11-dBm third-order input intercept point (IIP3) over the full frequency range with a 0.9-V supply. The maximum power consumption is 10.6 mW.

A Compact 10-b SAR ADC With Unit-Length Capacitors and a Passive FIR Filter

This paper presents a compact 10-b successive approximation register analog-to-digital converter (SAR ADC) in 65-nm CMOS with an integrated passive finite impulse response (FIR) filter for anti-aliasing. Conventional switched-capacitor digital-to-analog converters (DACs) are usually implemented with unit elements for the best matching performance, at the cost of increased chip area. Instead, this paper proposes a unit-length capacitor implementation, which minimizes the number of components and thus minimizes area, while also achieving good linearity (integral non-linearity of 0.39 LSB, differential non-linearity of 0.55 LSB, and SFDR of 75 dB) despite using a small LSB capacitor of 125 aF. The 10-b SAR ADC occupies only $36 \times 36\,\,\mu \text{m}$ , thanks to the small-size DAC, and by placing the ADC circuits directly under the capacitors. The ADC was tested at 10 and 30 MS/s and achieves an effective number of bits of 9.18/9.10 bit with an figure-of-merit of 4.1/4.4 fJ per conversion-step, respectively. Besides the ADC, a passive analog FIR filter is added to implement an anti-aliasing filter. The topology is based on a passive charge-sharing network and thus only consumes power for the clock phase generation and switch drivers. A 4 $\times $ time-interleaved 15-tap passive FIR filter is implemented, which can realize >42 dB out-of-band rejection and 4 $\times $ decimation while occupying only $53\times 90\,\,\mu \text{m}$ . The filter and the ADC together consume 39.2 $\mu \text{W}$ for an output rate of 10 MS/s.

A 750-nW 1-MHz 9-tap analog finite impulse response filter for wireless senor network chip

This paper presents a low power Finite Impulse Response (FIR) filter based on discrete-time analog computing. The analog FIR filter is first presented to deal with analog signal. To improve linearity, two-double boost technique is introduced in the sample and hold cells which are used to achieve delay-time function. Meanwhile, the four-quadrant voltage-mode multiplier consists of PMOS substract cell and combiner cell, which is independent of device parameters. To realize the shift registers function, the rotating switch matrix circuit is adopted controlled by phase shift clocks. All MOS transistors implemented in this architecture are biased in subthreshold region with a supply voltage of 0.6 V to reduce the power consumption. Simulation results show that the analog FIR filter dissipates 750 nW at 1 MHz sample frequency and the effective number of bits of the proposed analog FIR filter is more than 7 bits. Compared to the conventional digital FIR filter, power consumption is reduced by 72.22% at 1 MHz in a 0.18μm CMOS process.

A low-power 170-MHz discrete-time analog FIR filter

A 170-MHz analog finite impulse response (FIR) filter operating from a single 3.3-V supply is described. The design has been fabricated in the HP 1.2-/spl mu/m CMOS process and has an area of 2.35 mm by 1.97 mm including bonding pads. This 9-tap filter dissipates 70 mW when operating at 170 MHz. The multipliers are implemented using multiplying digital-to-analog converters (MDAC's) with 6-b resolution.

A BiCMOS implementation of a 276 MS/s forward equalizer and 200 MS/s FDTS detector

An analog finite impulse response filter (FIR) and an analog fixed delay tree search (FDTS) tau=l detector suitable for disk drive applications are presented. The FIR uses a rotary architecture with interleaved operation which allows clock rates up to 276 MS/s to be used. The FIR has seven taps, all programmable to six bit weights, and is implemented in fully differential form. The detector operates with clock rates up to 200 MS/s with no code restrictions. It makes use of a reduced minimum mean square error equation set to simplify the detector. Dual feedback filters are also used to shorten the critical path. A seven tap feedback filter is used with six bits of resolution per tap. The FIR consumes 180 mW while the detector uses 270 mW. The die size including all test buffers for the FIR and detector is 5.2 mm/sup 2/.

A CMOS IF transceiver with reduced analog complexity

Signal processing techniques are used to minimize the analog complexity in an intermediate-frequency (IF) transceiver. The receiver digitizes the IF signal directly by subsampling and complex bandpass delta-sigma modulation. A new loop filter is proposed for use in the complex delta-sigma. Digital demodulation and filtering are then used to extract the baseband information. The transmit section converts baseband to IF through an all-digital signal path. A bandpass delta-sigma modulator quantizes the digital IF signal to 1 bit in order to simplify the IF output digital-to-analog converter/driver. The output driver provides analog finite impulse response filtering for quantization noise.