Analog Convolution Research Articles

Compact lensless convolution processor for an optoelectronic convolutional neural network

To our knowledge, optical 4f systems have been widely used as a convolutional layer to perform convolutional computation in free-space optical neural networks (ONNs), which makes ONNs too bulky to be easily applied to miniaturized smart systems. Hence, we propose a compact lensless optoelectronic convolutional neural network (LOE-CNN) architecture in which a single optimized diffractive phase mask acts as an analog convolution processor to perform convolutional operation without a Fourier lens or lenslet array. We demonstrate that this LOE-CNN can be functionally comparable to existing electronic counterparts in classification performance, achieving a classification accuracy of 98.07% and 95% over the Modified National Institute of Standards and Technology dataset in simulation and experiment, respectively, which not only opens new application prospects for free-space ONNs based on a compact single-chip convolution processor, but also facilitates the development of ONN-based smart devices.

Design of an Always-On Image Sensor Using an Analog Lightweight Convolutional Neural Network

This paper presents an always-on Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) using an analog convolutional neural network for image classification in mobile applications. To reduce the power consumption as well as the overall processing time, we propose analog convolution circuits for computing convolution, max-pooling, and correlated double sampling operations without operational transconductance amplifiers. In addition, we used the voltage-mode MAX circuit for max pooling in the analog domain. After the analog convolution processing, the image data were reduced by 99.58% and were converted to digital with a 4-bit single-slope analog-to-digital converter. After the conversion, images were classified by the fully connected processor, which is traditionally performed in the digital domain. The measurement results show that we achieved an 89.33% image classification accuracy. The prototype CIS was fabricated in a 0.11 μm 1-poly 4-metal CIS process with a standard 4T-active pixel sensor. The image resolution was 160 × 120, and the total power consumption of the proposed CIS was 1.12 mW with a 3.3 V supply voltage and a maximum frame rate of 120.

12-разрядный безконденсаторный КМОП-АЦП с КНИ-структурой и напряжением питания 1,8 В±5%

Considered architecture CMOS ADC with digital forecasting input analog signal and converted education error signal sectional ADCS from analog convolution. It is shown that 12-bit CMOS ADC with project standards 0.18 micron provides high accuracy and speed of conversion to 600...1000 million samples/s when operating in hard conditions. Noted that through simple modifications considered architecture can increase the bit CMOS ADC to 14 bits.

Discretization of continuous convolution operators for accurate modeling of wave propagation in digital holography

Discretization of continuous (analog) convolution operators by direct sampling of the convolution kernel and use of fast Fourier transforms is highly efficient. However, it assumes the input and output signals are band-limited, a condition rarely met in practice, where signals have finite support or abrupt edges and sampling is nonideal. Here, we propose to approximate signals in analog, shift-invariant function spaces, which do not need to be band-limited, resulting in discrete coefficients for which we derive discrete convolution kernels that accurately model the analog convolution operator while taking into account nonideal sampling devices (such as finite fill-factor cameras). This approach retains the efficiency of direct sampling but not its limiting assumption. We propose fast forward and inverse algorithms that handle finite-length, periodic, and mirror-symmetric signals with rational sampling rates. We provide explicit convolution kernels for computing coherent wave propagation in the context of digital holography. When compared to band-limited methods in simulations, our method leads to fewer reconstruction artifacts when signals have sharp edges or when using nonideal sampling devices.

All-optical Multiplication with the help of Semiconductor Optical Amplifier—assisted Sagnac Switch

An all-optical two 2-bit numbers multiplication with the help of Semiconductor Optical Amplifier (SOA)—assisted Sagnac Switch is proposed and described. The paper describes the multiplication using a set of all-optical half-adder and AND gate. Because of the lack of fast, accurate, and large dynamic range analog-to-digital converter, optical implementation of the digital multiplication through analog convolution algorithm yields a slow digital multiplier. By using a set of optical half-adder and optical AND, a new optical fast digital multiplication method is proposed. The new method promises both higher processing speed and accuracy. Numerical simulation result confirming described methods and conclusion are given in this paper.

Optoelectronic array processor for identifying holograms with encoded latent images

This paper discusses methods of coding latent images in protective holograms in order to increase their degree of protection from counterfeiting and to automate the monitoring of their authenticity. It is proposed to use the operation of vector-matrix multiplication as a coding-decoding algorithm, carried out on optical signals by digital multiplication by means of analog convolution. Possible optical layouts for implementing the chosen algorithm are analyzed.

Cellular νMOS Circuits Performing Edge Detection with Difference-of-Gaussian Filters

Aiming at the development of high-speed image processors, we propose a cellular νMOS circuit that performs the processing of edge detection. The proposed circuit uses neuron MOS (νMOS) transistors for analog convolution operations with Gaussian-shaped kernel functions, which makes the circuit organization extremely simple as compared with that of conventional convolution circuits. Performances of the proposed circuit are evaluated by simulation program with integrated circuit emphasis (SPICE). The results show the usefulness of the cellular νMOS circuit in image-processing applications.

Fiber-optic array algebraic processing architectures

A high-accuracy fiber-optic array processor (FOAP) based on the algorithm of digital multiplication by analog convolution is proposed. The FOAP architecture is a local regularly interconnected processor that utilizes an array of identical all-optical elemental-processing lattice units, namely, an optical splitter, an optical combiner, and a binary programmable fiber-optic transversal filter. Various FOAP matrix multipliers are proposed for nonnegative and twos-complement binary arithmetic matrix-vector, matrix-matrix, triple-matrix, and high-order matrix operations. The overall performances of the FOAP matrix multipliers are compared with the time-integrating and space-integrating architectures and with the digital multipliers. Extension of the digital-multiplication-by-analog-convolution algorithm is also considered.

Matrix–vector multiplication using digital partitioning for more accurate optical computing

Digital partitioning offers a flexible means of increasing the accuracy of an optical matrix-vector processor. This algorithm can be implemented with the same architecture required for a purely analog processor, which gives optical matrix-vector processors the ability to perform high-accuracy calculations at speeds comparable with or greater than electronic computers as well as the ability to perform analog operations at a much greater speed. Digital partitioning is compared with digital multiplication by analog convolution, residue number systems, and redundant number representation in terms of the size and the speed required for an equivalent throughput as well as in terms of the hardware requirements. Digital partitioning and digital multiplication by analog convolution are found to be the most efficient algorithms if coding time and hardware are considered, and the architecture for digital partitioning permits the use of analog computations to provide the greatest throughput for a single processor. To our knowledge this is the first study to propose the use of digital partitioning for optical matrix processing.

Highly parallel architecture for optical disk database correlation with compensation for database errors

Architectural prototypes and algorithms for performing many simultaneous complex correlations between external data and data stored on optical disks are presented. External data are modulated onto an addressing light beam acoustooptically. Analog correlation outputs are obtained at low bandwidth. Data may be encoded on the disk either digitally, and correlated by using a digital multiplication by analog convolution scheme, or by analog area modulation. Bipolar correlations are shown possible without data biasing when two auxilliary diode lasers are used in a sign determination scheme. Error issues include variations in reflectances of encoded bits and raw disk errors.

Fast digital optical multiplication using an array of binary symmetric logic counters

Because of the lack of fast, accurate, and large dynamic range analog-to-digital converters (ADCs), optical implementation of the digital multiplication through analog convolution (DMAC) algorithm yields a slow digital multiplier. By replacing both the optical adder and ADC arrays by an optical combinatorial logic counter array, a new optical fast digital multiplication method is proposed. Compared to the existing optical DMAC scheme, the new method promises both higher processing speed and accuracy. A comparison of this and some of the other optical and electronic fast digital multiplication schemes is also presented.

Optical analog to digital converter using optical logic and table look-up

The need for high performance analog to digital (AID) converters, the advantages of optics, and current approaches to AID conversion are reviewed. A novel method, for which a U.S. patent was recently awarded, is proposed that uses comparators, optical logic, and a table look-up to provide optical digital output from an optical analog input. The advantage of the new method is the ability to produce any digital code, optical input! output, and longer word lengths at high speed. Implementations of the optical logic are proposed that use 1-D spatial light modulator devices under development, including self-electro-optic effect devices (SEEDs), double heterostructure optoelectronic switch (DOES) devices, and spatial light rebroadcasters (SLRs). Optical AID converters could make digital multiplication by analog convolution competitive with electronic systems.

Programmable fiber/integrated-optics bipolar tap

A programmable bipolar tap implementation is described. The proposed scheme utilizes fiber and integrated-optics technology in conjunction with twos complement number representation and digital multiplication by an analog convolution algorithm. Simple experimental verification of the scheme is presented.

Fiber-optic bipolar tap implementation using an incoherent optical source

A fiber-optic bipolar tap implementation is described. The proposed scheme utilizes 2's complement-number representation and digital multiplication by an analog convolution algorithm. Simple experimental verification of the scheme is presented. The addition of programmability to the taps results in the realization of a fast, flexible processor for manipulating binary quantities.

High accuracy computation with linear analog optical systems: a critical study

High accuracy optical processors based on the algorithm of digital multiplication by analog convolution (DMAC) are studied for ultimate performance limitations. Variations of optical processors that perform high accuracy vector-vector inner products are studied in abstract and with specific examples. It is concluded that the use of linear analog optical processors in performing digital computations with DMAC leads to impractical requirements for the accuracy of analog optical systems and the complexity of postprocessing electronics.

Asynchronous integrated optical multiply accumulate with sideways summer

An asynchronous method of implementing the digital multiplication by analog convolution algorithm is presented. The mixed binary output is formed in one switching time regardless of the number of bits in the word. Novel circuitry that logarithmically reduces the number of shift and add levels is shown.

Negative base encoding in optical linear algebra processors

In the digital multiplication by analog convolution algorithm, the bits of two encoded numbers are convolved to form the product of the two numbers in mixed binary representation; this output can be easily converted to binary. Attention is presently given to negative base encoding, treating base -2 initially, and then showing that the negative base system can be readily extended to any radix. In general, negative base encoding in optical linear algebra processors represents a more efficient technique than either sign magnitude or 2's complement encoding, when the additions of digitally encoded products are performed in parallel.

Photonic Computing Using The Modified Signed-Digit Number Representation

Improving the precision of optically performed computations is a critical aspect of photonic computing. One possible method for improving precision is through the use of modified signed-digit (MSD) arithmetic. Optical implementation of MSD arithmetic offers several important advantages over other optical techniques such as the digital multiplication by analog convolution (DMAC) algorithm or the use of residue arithmetic. These advantages include the parallel pipeline flow of digits due to carry-free addition and subtraction, fixed-point as well as floating-point capability, and the potential for performing divisions. We present a brief description of the modified signed-digit number system and suggest one optical architecture for implementing MSD fixed-point addition, subtraction, and multiplication.

A space integrating acousto-optic matrix-matrix multiplier

An optical architecture is described for performing pipelined matrix-matrix multiplications. The architecture is implemented using multiple transducer acousto-optic devices and a wideband photodetector array. A variant of engagement formatting allows multiple inner products to be simultaneously computed by 1-D spatial integration, and through proper pipelining the full product matrix is produced at the output of the detector array. The output matrix in this architecture is in a format that is directly compatible with the input, a feature that can facilitate the implementation of iterative matrix algorithms. Digital multiplication by analog convolution can be incorporated for improved accuracy by using a frequency multiplexed representation of the binary data.

Binary space-integrating acousto-optic processor for vector-matrix multiplication

A binary acousto-optic processor for high accuracy vector-matrix multiplication is described. The processor's operation is based on the formation of inner products. Digitsl products are formed via analog convolution. A spherical lens is used to form both the necessary convolution integral as well as the summation of different digital products. The resulting system requires a single detector for inner product detection. The processor's performance and characteristics are discussed along with possible solutions for performance improvements.