Analog Complementary Metal Oxide Semiconductor Research Articles

Improved circuitry and post-processing for interleaved fast-scan cyclic voltammetry and electrophysiology measurements

The combination of electrophysiology and electrochemistry acquisition methods using a single carbon fiber microelectrode (CFM) in the brain has enabled more extensive analysis of neurochemical release, neural activity, and animal behavior. Predominantly, analog CMOS (Complementary Metal Oxide Semiconductor) switches are used for these interleaved applications to alternate the CFM output between electrophysiology and electrochemistry acquisition circuitry. However, one underlying issue with analog CMOS switches is the introduction of transient voltage artifacts in recorded electrophysiology signals resulting from CMOS charge injection. These injected artifacts attenuate electrophysiology data and delay reliable signal observation after every switch actuation from electrochemistry acquisition. Previously published attempts at interleaved electrophysiology and electrochemistry were able to recover reliable electrophysiology data within approximately 10–50 ms after switch actuation by employing various high-pass filtering methods to mitigate the observed voltage artifacts. However, high-pass filtering of this nature also attenuates valuable portions of the local-field potential (LFP) frequency range, thus limiting the extent of network-level insights that can be derived from in vivo measurements. This paper proposes a solution to overcome the limitation of charge injection artifacts that affect electrophysiological data while preserving important lower-frequency LFP bands. A voltage follower operational amplifier was integrated before the CMOS switch to increase current flow to the switch and dissipate any injected charge. This hardware addition resulted in a 16.98% decrease in electrophysiology acquisition delay compared to circuitry without a voltage follower. Additionally, single-term exponential modeling was implemented in post-processing to characterize and subtract remaining transient voltage artifacts in recorded electrophysiology data. As a result, electrophysiology data was reliably recovered 3.26 ± 0.22 ms after the beginning of the acquisition period (a 60% decrease from previous studies), while also minimizing LFP attenuation. Through these advancements, coupled electrophysiology and electrochemistry measurements can be conducted at higher scan rates while retaining data integrity for a more comprehensive analysis of neural activity and neurochemical release.

Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs

The design and optimization of the analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are intrinsically complicated and depend heavily on the designer’s experience, and are associated with very long design and optimization-cycle times. In addition, in order to the analog and radiofrequency (RF) CMOS IC work suitably in practice, it is necessary to perform robustness analyses (RAs) through Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, which result in still-higher design and optimization cycle times and therefore represent the biggest bottleneck to the launching of new electronic products. In this context, this manuscript aims to present, for the first time, the use of a custom imperialist competitive algorithm (ICA) in order to reduce the design and optimization-cycle times of analog CMOS ICs. In this study, we implement some Miller CMOS operational transconductance amplifiers (OTAs) using the computational tool named iMTGSPICE, considering two different bulk CMOS IC manufacturing processes from Taiwan Semiconductor Company (TSMC) (180 nm and 65 nm nodes) and two evolutionary optimization methodologies of artificial intelligence, i.e., ICA and a genetic algorithm (GA). The main result obtained by this work shows that, by using an ICA-customized evolutionary algorithm to perform the design and optimization processes of Miller CMOS OTAs, it is possible to reduce the design and optimization-cycle times by up to 83% in relation to those implemented with the GA-customized evolutionary algorithm, achieving practically the same electrical performance.

Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs

Previous studies have been showing that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal) and Ellipsoidal gate shapes for implementing of the planar and three-dimensional MOSFETs are is capable of boosting their analog and digital electrical performances and also by reducing used die areas, when we replace conventional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), that present rectangular gate shape, by those implemented by these innovative layout styles. In order to further boosting these features obtained by the use of first generation of layout styles, we are introducing one of elements of the second generation of layout styles for MOSFETs, intitled Half-Diamond. This new proposal is an evolution of Diamond layout style, in which it is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects of the first generation and also of further reducing the dimensions of conventional MOSFETs (CM) in which the Diamond MOSFETs have gotten to do. Thus, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond and Conventional layout styles, regarding the analog Complementary MOS (CMOS) integrated circuits (ICs) applications, which their channel lengths are not usually designed with the minimum dimension (Lmin) allowed by the CMOS ICs manufacturing processes. The results obtained show that, for instance, the saturation drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in CM counterparts. Besides, by using Half-Diamond layout style, it is possible of further reducing the die areas of analog CM and consequently of the analog CMOS ICs applications, in comparison to those reached by the use of Diamond layout styles, regarding a 180 nm Bulk CMOS ICs technology node.

A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits.

To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation.

Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs

This paper describes a pioneering methodology to design, optimize, and reduce the total gate area of robust Operational Transconductance Amplifiers (OTAs). The Single-Ended Single-Stage (SESS) OTA has been chosen to validate the proposed technique by using the 180 nm planar Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technology. The Electronic Design Automationtool, named iMTGSPICE, was used to design and optimize the SESS OTA. There are several heuristics optimization techniques of Artificial Intelligence to optimize analog and radio-frequency CMOS ICs, but we have selected to use the Genetic Algorithm because it presents the best optimization performance among the other algorithms previously studied. This paper also describes a procedure of converting the Conventional planar MOSFETs (rectangular gate shape) into the Diamond MOSFETs (hexagonal gate shape) with the same electrical performance. Furthermore, it is proposed a procedure to simulate the Diamond MOSFETs (DMs) in the Simulation Program with Integrated Circuit Emphasis (SPICE) because there is still no SPICE model to perform the DM. Additionally, this work proposes a methodology to layout OTAs with Diamond MOSFETs, regarding different values of aspect ratios. The main result of this work reveals a total gate area reduction of approximately 30% of a robust OTA implemented with Diamond MOSFETs, with an alpha angle (α) equal to 45°, with respect to the one observed in the robust OTA implemented with standard MOSFETs, maintaining practically the same electrical performance and robustness.

Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This article describes an experimental comparative study of the matching between the Octo conventional (octagonal gate geometry) and Conventional (rectangular gate shape) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology and exposed to different X-rays Total Ionizing Doses (TIDs), under the on-state bias conditions. The results indicate that the Octo layout style with alpha ( $\alpha $ ) angle equal to 90° and a cut factor of 50% for MOSFETs is capable of boosting the device matching by at least 56.1%, on average, regarding the electrical parameters studied (Threshold Voltage and Subthreshold Swing), as compared to those found in the Conventional MOSFET counterparts, considering that they present the same bias conditions and regarding different TIDs. This happens due to the Longitudinal Corner Effect (LCE), Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) which are present in the Octo MOSFETs. Therefore, the Octagonal layout style can be considered as an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS ICs applications.

Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with alpha () angle equal to 90˚ for MOSFETs is capable of boosting the device matching by at least 17% regarding the electrical pa-rameters studied (Threshold Voltage and Subthreshold Slope) as compared with the conventional MOSFET counterparts, considering that they present the same gate area, channel width, bias conditions and for the same TID. This is due to the Longitudinal Corner Effect (LCE). Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) present in the structure of Diamond MOSFETs. Therefore, the Diamond layout style can be consid-ered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS inte-grated circuits (ICs) applications.

Analog Complementary Metal-Oxide-Semiconductor Integrate-and-Fire Neuron Circuit for Overflow Retaining in Hardware Spiking Neural Networks.

The spiking neural network (SNN) is regarded as the third generation of an artificial neural network (ANN). In order to realize a high-performance SNN, an integrate-and-fire (I&F) neuron, one of the key elements in an SNN, must retain the overflow in its membrane after firing. This paper presents an analog CMOS I&F neuron circuit for overflow retaining. Compared with the conventional I&F neuron circuit, the basic operation of the proposed circuit is confirmed in a circuit-level simulation. Furthermore, a single-layer SNN simulation was also performed to demonstrate the effect of the proposed circuit on neural network applications by comparing the raster plots from the circuit-level simulation with those from a high-level simulation. These results demonstrate the potential of the I&F neuron circuit with overflow retaining characteristics to be utilized in upcoming high-performance hardware SNN systems.

A Comprehensive Comparison of EMI Immunity in CMOS Amplifier Topologies

This paper provides the results of a comprehensive comparison between complementary metal oxide semiconductor (CMOS) amplifiers with low susceptibility to electromagnetic interference (EMI). They represent the state-of-the-art in low EMI susceptibility design. An exhaustive scenario for EMI pollution has been considered: the injected interference can indeed directly reach the amplifier pins or can be coupled from the printed circuit board (PCB) ground. This is also a key point for evaluating the susceptibility from EMI coupled to the output pin. All of the amplifiers are re-designed in a United Microelectronics Corporation (UMC) 180 nm CMOS process in order to have a fair comparison. The topologies investigated and compared are basically derived from the Miller and the folded cascode ones, which are well-known and widely used by CMOS analog designers.

A Charge Amplifier Based Complementary Metal–Oxide–Semiconductor Analog Front End for Piezoelectric Microphones in Hearing Aid Devices

In this paper, a low noise and low power analog front end for piezoelectric microphones used in hearing aid devices is presented. It consists of a Charge Amplifier, followed by a Variable Gain Amplifier and an Analog-to-Digital Converter. At the core of charge amplifier a two stage opamp with modified cascode current mirror is designed which achieves a gain of 93 dB and phase margin of 62°. Designed analog front end achieves an input referred noise of 0.12 μVrms and SNR of 74 dB. It consumes power of 430 μW from 1.8 V supply and occupies an area of 1.2 mm × 0.22 mm. Proposed circuit is designed and fabricated in 0.18 μm CMOS process. Designed circuit is interfaced with a sensor model of piezoelectric microphone, which mimics Ormia ochracea's auditory system, and its performance is successfully verified against simulation results.

A customized genetic algorithm with in-loop robustness analyses to boost the optimization process of analog CMOS ICs

The traditional optimization processes of analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are very complex, slow, and based on the designers’ experience. To obtain robust potential solutions, it is necessary to perform robustness analyses (RAs) through SPICE simulations. However, this approach represents a huge bottleneck in the optimization processes due to the significant increase of time of the SPICE simulations concerning the RAs. Therefore, this work proposes an innovative customized genetic algorithm (GA) to boost the optimization process of analog CMOS ICs. The main results obtained showed that all designs of analog CMOS ICs reached a yield of 100% and a remarkable reduction of the optimization time (from 23% to 79%) in comparison with the standard optimization process with the GA, without reducing the random samples number considered in the RAs, and consequently preserving their robustness accuracy.

Bendable CMOS Digital and Analog Circuits Monolithically Integrated with a Temperature Sensor

Flexible electronics is now one of key technologies for electronic devices that collect information from nonplanar surfaces, ultimately enabling the realization of the trillion sensor concept and the internet of things. Both flexible discrete devices and sensors are required for integration of digital and analog circuits for signal processing. In this study, flexible, energy efficient, complementary metal‐oxide‐semiconductor (CMOS) digital and analog circuits, monolithically integrated with a temperature sensor are reported: This is achieved by developing the process of p‐type and n‐type transistors on a flexible substrate. For the digital circuits, CMOS‐based J–K flip‐flop circuits are fabricated on a polyimide substrate, and testing confirms that they can be operated under mechanical bending without malfunction. Furthermore, the fabrication of a flexible analog differential amplifier is demonstrated, with the device successfully amplifying the output of an integrated temperature sensor by ≈38 times. Although these demonstrations are still at the proof‐of‐concept stage for flexible signal processing circuits, these achievements are a key step toward the next level of device integration, thereby enabling the development of viable flexible electronic devices.

Total ionizing dose radiation effects in foue-transistor complementary metal oxide semiconductor image sensors

Radiation effects on four-transistor (4 T) active pixel sensor complementary metal-oxide-semiconductor (CMOS) image sensor induced by -ray are presented. The samples are 4 megapixels resolution CMOS image sensor using 11 upm pitch high dynamic 4 T pixels. They are manufactured with 0.18 upm specialized CMOS image sensortechnology. Three samples have been exposed to 200 krad(Si) 60Co -ray with different biasing condition (1# is static-biased, 2# dynamic-biased, and 3# is grounded during irradiation), and the dose rate is 50 rad(Si)/s. The influences of radiation on full well charge capacity, dark current, and conversion gain of the device are investigated. Experimental result shows that the conversion gain is not sensitive to the ionizing radiation, and it is mainly determined by the CMOS digital or analog circuits. It is known that the total ionizing dose for induced degradation in deep submicron MOSFET is negligible and so there is almost no radiation effect on the digital or analog circuits exposed to the ionizing radiation. Therefore, conversion gain does not have obvious degradation after irradiation. While full well charge capacity has a degradation after irradiation, which is due to the change of TG channel doping profile induced by the radiation. As the dose increases, dark current increases rapidly. The main source of dark current in 4 T CMOS image sensor is the current from STI interface and TG-PD overlap region. Experimental result also shows that different from 3 T CMOS image sensor, there is no biasing effect in 4 T CMOS image sensor. This is because for the 4 T CMOS image sensor most of the degradation come from STI interface and TG-PD overlap region, while biasing condition almost has no influence on both ofthem.

Electrical behavior of the Diamond layout style for MOSFETs in X-rays ionizing radiation environments

This paper aims to describe some innovative layout styles, which are capable to boost the electrical performance and, in the same time, the Total Ionizing Dose (TID) tolerance of Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), without burdening the current planar Complementary MOS (CMOS) Integrated Circuits (ICs) manufacturing processes. To illustrate the potential use of these new alternative devices in analog and digital CMOS ICs applications, this work focuses on the Diamond layout style for MOSFET that presents hexagonal gate geometry. The new effects associated to this innovative transistor structure and its modeling are presented and discussed in detail. Some experimental results are illustrated to evidence its use mainly in space and medical CMOS ICs applications.

Optimal sizing of CMOS analog circuits using gravitational search algorithm with particle swarm optimization

In this paper, a hybrid population based meta-heuristic search algorithm named as gravitational search algorithm (GSA) combined with particle swarm optimization (PSO) (GSA–PSO) is proposed for the optimal designs of two commonly used analog circuits, namely, complementary metal oxide semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier circuit. PSO and GSA are simple, population based robust evolutionary algorithms but have the problem of suboptimality, individually. The proposed GSA–PSO based approach has overcome this disadvantage faced by both the PSO and the GSA algorithms and is employed in this paper for the optimal designs of two amplifier circuits. The transistors’ sizes are optimized using GSA–PSO in order to minimize the areas occupied by the circuits and to improve the design/performance parameters of the circuits. Various design specifications/performance parameters are optimized to optimize the transistor’s sizes and some other design parameters using GSA–PSO. By using the optimal transistor sizes, Simulation Program with Integrated Circuit Emphasis simulation has been carried out in order to show the performance parameters. The simulation results justify the superiority of GSA–PSO over differential evolution, harmony search, artificial bee colony and PSO in terms of convergence speed, design specifications and performance parameters of the optimal design of the analog CMOS amplifier circuits. It is shown that GSA–PSO based design technique for each amplifier circuit yields the least MOS area, and each designed circuit is shown to have the best performance parameters like gain, power dissipation etc., as compared with those of other recently reported literature. Still the difficulties and challenges faced in this work are proper tuning of control parameters of the algorithms GSA and PSO, some conflicting design/performance parameters and design specifications, which have been partially overcome by repeated manual tuning. Multi-objective optimization may be the proper alternative way to overcome the above difficulties.

A biophysically-based neuromorphic model of spike rate- and timing-dependent plasticity

Current advances in neuromorphic engineering have made it possible to emulate complex neuronal ion channel and intracellular ionic dynamics in real time using highly compact and power-efficient complementary metal-oxide-semiconductor (CMOS) analog very-large-scale-integrated circuit technology. Recently, there has been growing interest in the neuromorphic emulation of the spike-timing-dependent plasticity (STDP) Hebbian learning rule by phenomenological modeling using CMOS, memristor or other analog devices. Here, we propose a CMOS circuit implementation of a biophysically grounded neuromorphic (iono-neuromorphic) model of synaptic plasticity that is capable of capturing both the spike rate-dependent plasticity (SRDP, of the Bienenstock-Cooper-Munro or BCM type) and STDP rules. The iono-neuromorphic model reproduces bidirectional synaptic changes with NMDA receptor-dependent and intracellular calcium-mediated long-term potentiation or long-term depression assuming retrograde endocannabinoid signaling as a second coincidence detector. Changes in excitatory or inhibitory synaptic weights are registered and stored in a nonvolatile and compact digital format analogous to the discrete insertion and removal of AMPA or GABA receptor channels. The versatile Hebbian synapse device is applicable to a variety of neuroprosthesis, brain-machine interface, neurorobotics, neuromimetic computation, machine learning, and neural-inspired adaptive control problems.

Two High-Speed and Large-Drive-Current BiCMOS Analog Switches

In order to obtain high-speed and large-drive-current during operation, this paper proposed two structure-advanced BiCMOS analog switches. On the key parts of the circuit, a few Bipolar Junction Transistors (BJTs) were used while for the main parts, the Complementary Metal Oxide Semiconductor (CMOS) devices were configured. The component parameters were optimized and the measures for accelerating the operation and raising the drive-current were taken. The performance of the proposed two analog switches was tested through simulation and experiments of hardware circuits. The results indicated that the Delay-Power Product (DP) of the BiCMOS operating in the voltage range of 2.5V~3.5V is reduced by an average of 26.1pJ and the driving current is more than 1.38mA as compared with those of the conventional CMOS analog switches. These advantages show the great potential of the proposed two BiCMOS analog switches in the digital communication systems which require low-voltage, high-speed and large-drive-current.

Analog Circuit Design in Nanoscale CMOS Technologies

As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The condition <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vsb</i> > 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, as <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vsb</i> > 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters.

Simple Analog Complementary Metal Oxide Semiconductor Circuit for Generating Motion Signal

We proposed in this study a novel analog complementary metal oxide semiconductor (CMOS) circuit for generating a motion signal when an object moves, which is a simple structure. The proposed unit circuit was constructed using a previously proposed edge detection circuit and a novel proposed circuit for generating a motion signal which accepts an edge signal. The part for generating the motion signal was constructed using six metal oxide semiconductor (MOS) transistors and one capacitor. Results obtained by the simulation program with integrated circuit emphasis (SPICE) and the measured results of a test circuit constructed with discrete MOS transistors and the test circuit fabricated with a 1.2 μm CMOS process showed that the proposed unit circuit can output pulsed current (motion signal) when an object moves on the circuit. It was clarified from the SPICE results that the two-dimensional network constructed with proposed unit circuits can output motion signals. The size of the novel unit circuit is expected to be about 110 × 110μm2 obtained by the 1.2 μm CMOS process. It is possible to arrange 90 × 90 unit circuits on a chip which has an area of 1 × 1cm2. The aperture ratio is expected to be about 21%, which is twice as large as that of the previously proposed circuit. An integrated circuit for image processing in real time can thus be realized by applying the two-dimensional network constructed with the proposed circuits.

Analog Integrated Circuit for Motion Detection with Simple-Shape Recognition Based on Frog Vision System

We proposed in this research a novel two-dimensional network based on the frog visual system, with a motion detection function and a newly developed simple-shape recognition function, for use in object discrimination by integrated circuits. Specifically, the network mimics the signal processing of the small-field cell in a frog brain, consisting of the tectum and thalamus, which generates signals of the motion and simple shape of an object. The proposed network is constructed from simple analog complementary metal oxide semiconductor (CMOS) circuits; a test chip of the proposed network was fabricated with a 1.2 μm CMOS process. Measurements on the chip clarified that the proposed network can generate signals of the moving direction, velocity, and simple shape, as well as perform information processing of the small-field cell. Results with the simulation program with integrated circuit emphasis (SPICE) showed that the analog circuits used in the network have low power consumption. Applications of the proposed network are expected to realize advanced vision chips with functions such as object discrimination and target tracking.