Analog CMOS Technology Research Articles

A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning.

The memristor has been extensively used to facilitate the synaptic online learning of brain-inspired spiking neural networks (SNNs). However, the current memristor-based work can not support the widely used yet sophisticated trace-based learning rules, including the trace-based Spike-Timing-Dependent Plasticity (STDP) and the Bayesian Confidence Propagation Neural Network (BCPNN) learning rules. This paper proposes a learning engine to implement trace-based online learning, consisting of memristor-based blocks and analog computing blocks. The memristor is used to mimic the synaptic trace dynamics by exploiting the nonlinear physical property of the device. The analog computing blocks are used for the addition, multiplication, logarithmic and integral operations. By organizing these building blocks, a reconfigurable learning engine is architected and realized to simulate the STDP and BCPNN online learning rules, using memristors and 180 nm analog CMOS technology. The results show that the proposed learning engine can achieve energy consumption of 10.61 pJ and 51.49 pJ per synaptic update for the STDP and BCPNN learning rules, respectively, with a 147.03× and 93.61× reduction compared to the 180 nm ASIC counterparts, and also a 9.39× and 5.63× reduction compared to the 40 nm ASIC counterparts. Compared with the state-of-the-art work of Loihi and eBrainII, the learning engine can reduce the energy per synaptic update by 11.31× and 13.13× for trace-based STDP and BCPNN learning rules, respectively.

Study and Design of 40 nW CMOS Temperature Sensor for Space Applications

In this paper, a novel CMOS temperature sensors based on sub-threshold MOS operation has been presented, which is designed for space and satellite applications. This proposed CMOS temperature sensor is enunciated good linearity between temperatures range from -55 O C to 150 O C with inaccuracy of 0.85 O C/V. This circuit is operated at supply 1V and static power consumption 40nW is achieved. The proposed circuit is based on the MOS threshold voltage and mobility. There are two type of sensor output in presented circuit first, voltage proportional to absolute temperature (PTAT) due to threshold voltage and second, negative temperature coefficient (NTC) due to mobility. This circuit is designed & simulated using Cadence analog & digital system design tools UMC90nm CMOS technology. The layout area of the circuit is 17.213μm 6.655μm. This is a low power and longer battery life for harsh environment, wireless sensor network applications etc.

NEMS Switches Monolithically Fabricated on CMOS MIM Capacitors

Abstract This work demonstrates the monolithically integration of NEMS structures in a commercial CMOS technology. Low voltage operating switches (5 V) have been obtained thanks to the definition of a small structure (1.5 μm length, 500 nm width) and a small gap (27 nm), using the MIM module of an analog CMOS technology (AMS 0. 35 μm). In this way NEMS can be fabricated taking advantage of the robust and reproducible CMOS fabrication process.

A 90-nm CMOS Threshold-Compensated RF Energy Harvester

This paper presents an efficient energy harvester for RF-powered sensor networks. The circuit is based on an improved multi-stage rectifier, which exploits a fully passive threshold self-compensation scheme to overcome the limitation due to the input dead zone. A CAD-oriented design methodology is also proposed, which is aimed at maximizing the overall power conversion efficiency of the harvester through an optimum trade-off among matching losses, power reflection and rectifier efficiency. According to the proposed methodology, a 915-MHz harvester comprising an integrated input matching network and a 17-stage self-compensated rectifier has been designed and fabricated in a 90-nm CMOS technology. The rectifier exhibits a remarkably low input power threshold, as it is able to deliver a 1-V dc output voltage to a capacitive load with a very small input power of -24 dBm (4 μW). When driving a 1-MΩ load, the device can supply a 1.2-V output with an input power of -18.8 dBm (13.1 μW). The achieved results exceed the performance of previously reported RF multi-stage rectifiers in standard analog CMOS technology.

Design and test challenges in Nano-scale analog and mixed CMOS technology

Design and test challenges in Nano-scale analog and mixed CMOS technology

Two op-amps third-order sigma–delta modulator with 61-dB SNDR, 6-MHz bandwidth and 6-mW power consumption

This low-power $$\Sigma\Delta$$ modulator targets the DVB-H requirements and achieves about 10 bit with 6-MHz signal band. Suitable topological modifications enable the realization of a third order modulator with two op-amps. Moreover, a technique for swing reduction of the last op-amp strongly reduces the number of comparators in the quantizer. The power reduction techniques limit the consumption to 6.18 mW, thus yielding a FoM of 0.58 pJ/conversion. The area of the circuit, fabricated with a 0.18-μm analog CMOS technology, is 0.32 mm2. Experimental measurements confirm the behavioral study made accounting for the op-amps limitations.

A central pattern generator circuit for rhythmic robotic chewing locomotion in low-voltage analog CMOS technology

It is well known that rhythmic animal locomotive behavior such as walking, running, swimming, and flying is driven by biological neural networks with a phase-locked oscillatory behavior called a central pattern generator (CPG). This article describes a CPG circuit for the locomotion control of rhythmic robotic chewing. A two-neuron CPG model, which is slightly modified from the Matsuoka oscillator model, was implemented in a low-voltage analog CMOS circuit using the IBM 130 nm CMOS technology. A new concept of a −3 dB rhythmic chewing bandwidth has been introduced to account for the time constants in the model. The significance of the −3 dB chewing bandwidth is that any effort by the animal to chew at a faster rate than the inherent chewing bandwidth of that animal is likely to result in a reduced chewing force. Compared with the digital implementation, the analog CPG consumes less power and occupies less silicon area. The analog CPG consists of compensated current-mode low-pass filters and current mirrors implementing the neurons, which are cross-connected by inhibitory synaptic links. There are two tonic sensory inputs, two internal states, and two adaptation outputs for muscles for the CPG circuit.

A 110 nA Voltage Regulator System With Dynamic Bandwidth Boosting for RFID Systems

This paper describes a voltage regulator system for ultra-low-power RFID tags (also called passive tags) in a 0.15 mum analog CMOS technology. These tags derive their power supply from the incoming RF energy through rectification instead of from a battery. The regulator is functional with just 110 nA current. Owing to the huge variation of the rectified voltage (by as much as tens of volts), voltage limiters and clamps are employed at various points along the regulation path. A limiter at the rectifier output clamps the rectifier voltage to a narrower range of 1.4 V. A fine-regulator, then, regulates the supply voltage close to a bandgap reference value of 1.25 V. The key aspect of this regulator is the dynamic bandwidth boosting that takes place in the regulator by sensing the excess current that is bypassed in the limter (during periods of excess energy) and increasing its bias current and hence bandwidth, accordingly. A higher bandwidth is necessary for quick recovery from line transients due to the burst nature of RF transmission, with a larger energy burst requiring a higher bandwidth to settle quickly without large line transients. The challenge of compensating such a regulator across various load currents and RF energy levels is described in this paper

Analog CMOS Circuit Design and Characterization for Optical Coherence Tomography Signal Processing

We have developed a custom analog CMOS circuit to perform the signal processing for an optical coherence tomography imaging system. The circuit is realized in a 1.5 microm low-noise analog CMOS technology. The circuitry extracts the Doppler frequency from the signal and electrically mixes this with the original signal to provide a filtered A-scan. The circuitry was used to produce a two-dimensional image of an onion.

TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology

The number of circuit design iterations due to electrostatic discharge (ESD) failures increases with the complexity of VLSI technologies and their shrinking. In this paper, we show how TCAD and ESD SPICE modeling can be used to solve ESD protection issues in an analog CMOS technology.

Microelectromechanical systems based on ferroelectric thin films

Ferroelectric thin films have been integrated in silicon-based microelectromechanical systems, commonly called MEMS. Several thin films of the PZT family have been used in the formation of both microsensors and microactuators in processes compatible with 2-μm analog CMOS technology. Ferroelectric MEMS offer significant advantages of high signal-to-noise, low power dissipation, and high force generation in comparison to other MEMS technologies such as those based on piezoresistive sensing and electrostatic actuation. While several concept feasibility demonstrations have been made to date in several areas, this paper will focus on the use of integrated, pyroelectric lead titanate thin films for infrared detection and integrated, piezoelectric lead zirconate titanate thin films for actuator applications.

On the relationship between topography and transistor matching in an analog CMOS technology

A source of drain current mismatch of transistors in a 1.75- mu m analog CMOS process is described. Matching of closely spaced transistors is degraded by capacitor topography created prior to the gate level. The effects extend over distances greater than 30 mu m and are not reduced by common-centroid layout techniques. Symmetry and wafer position dependencies of the mismatch lead to an explanation of the effect. The topography is thought to interfere with the radial flow of gate level photoresist as it is spun on the wafer. Thickness variations in the photoresist result in channel length variations in the transistors following patterning. Transistor matching is improved by more than a factor of two with the use of a tri-level photoresist sequence at the gate level. Simple theoretical expressions and more exact numerical simulations support the explanation of channel length differences as the source of the measured mismatch. These calculations suggest how mismatch due to channel length, dopant concentration, or gate-oxide thickness may be differentiated with simple current-voltage measurements. >

High-resolution low-power CMOS D/A converter

A very low-power, high-resolution, medium-speed D/A converter is described. The converter was realized using a standard analog CMOS technology. It achieved 15-bit monotonicity and less than 0.07-percent overall linearity at a clock frequency of 100 kHz, without requiring any trimming or calibration. The measured SNR was 85 dB, the power dissipation was less than 10 mW, and the distortion for a sinusoidal output was less than 0.04 percent. The D/A converter is intended for battery-powered speech and music synthesis applications where high dynamic range, low power, and low cost are all important. >