Common-mode Voltage Amplitude Research Articles

Modified SVPWM technique for CMV reduction in asymmetrical dual three phase induction machine drive

Due to its advantages, the asymmetrical dual three-phase induction motor drive is a strong choice in high-power applications. However, the common-mode voltage produced by the voltage source inverters affects the winding insulation and damages the bearings. Common-mode voltage is also responsible for electromagnetic interference and leakage currents. This paper, therefore, analyses the common-mode voltage produced by the inverter supplying a dual three-phase induction motor drive and proposes a novel modified space vector decomposition-based Space Vector Pulse Width Modulation (SVPWM) technique for common mode reduction. The vector space decomposition-based space vector modulation technique offers excellent flexibility as it reduces the common-mode voltage (CMV) by exploiting the additional degree of freedom in a dual three-phase system. The common-mode voltage (CMV) can be reduced to one-sixth of the DC link voltage compared to the highest CMV, i.e. half of the DC-link voltage produced in conventional space vector modulation. The proposed method is also validated experimentally to demonstrate the effectiveness of the proposed scheme in terms of the amplitude of CMV, pulsations, and total harmonic distortion(THD) in current.

Common-Mode Voltage Reduction for Back-to-Back Two-Level Converters Based on Zero-Sequence Voltage Injection

High frequency and high amplitude common-mode voltage (CMV) can induce a number of problems on the reliable operations of back-to-back two-level converters, such as shaft voltages and bearing currents. To restrain the CMV for back-to-back two-level converters, a simple and effective CMV reduction method based on zero-sequence voltage (ZSV) injection is proposed in this article. By injecting the optimal amount of ZSV on either the rectifier-side or the inverter-side, the corresponding pulse overlapping areas that result in high CMV amplitudes can be eliminated with the proposed method, then the amplitude of CMV can be reduced by half, and the pulse edges of CMV can be reduced by one-third. Simulation and experimental results are presented to verify the effectiveness of the proposed method in CMV reduction, while some comparisons are also conducted to demonstrate the superiority of the proposed method.

Low-frequency operation control method for medium-voltage high-capacity FC-MMC type frequency converter

The application of modular multilevel converters (MMCs) to large drive systems is subject to severe low-frequency operation restrictions. The fluctuation of capacitor voltage and the high amplitude of common mode voltage in sub-modules is a thorny problem. In this paper, a novel fly-across capacitor modular multilevel converter topology is adopted to eliminate low-frequency voltage ripples by using the fly-across capacitor as a power transfer channel between the upper and lower bridge arms of the MMC. A novel finite compensation method is proposed—instead of the traditional full compensation method—that introduces a real-time variable limiting factor to change the amplitude of the mixed injected high-frequency differential-mode voltage and high-frequency differential-mode current and reduce the amplitude of the common-mode voltage on the AC side while lowering the current stress of the power devices. Finally, a complete system simulation model is constructed, and the topology with the proposed control strategy are verified to have good output characteristics under different operating conditions; good results are achieved in suppressing the sub-module fluctuation and common-mode voltage.

Common-Mode Voltage Mitigation Strategies Using Sigma–Delta Modulation in Five-Phase VSIs

Various sigma–delta ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Sigma$</tex-math></inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Delta$</tex-math></inline-formula> ) modulation techniques for reducing the maximum peak-to-peak amplitude of common-mode voltage (CMV) by 80% in a five-phase, high-frequency voltage source inverter (VSI) are proposed and evaluated in this article. These techniques are based on choosing a set of vectors that limits the CMV amplitude. Operating the VSI under high-frequency pulsewidth modulations (PWM) generates a large number of changes in the CMV levels, which leads to common-mode currents (CMCs) and conducted electromagnetic interferences (EMIs). The proposed modulation techniques achieve the following: 1) High-efficiency converter operation and output voltage with low total harmonic distortion (THD); 2) an 80% reduction in CMV peak-to-peak amplitude; 3) a decrease in the number of the CMV transitions, thus reducing the CMCs; and 4) a decrease in the conducted EMI amplitude. The use of single-loop and double-loop <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Sigma$</tex-math></inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Delta$</tex-math></inline-formula> modulators is analyzed by means of Matlab/Simulink and PLECS simulations. The implementation of the proposed modulation techniques has been experimentally evaluated using a five-phase VSI with silicon carbide semiconductors. In order to demonstrate the improved performance, the results obtained are compared with those of other PWM and space vector modulation techniques that also mitigate the CMV amplitude by 80% but lack the other improvements.

Common-Mode Voltage Reduction and Neutral-Point Voltage Control Using Space Vector Modulation for Coupled Ten-Switch Three-Phase Three-Level Inverter

Space vector pulsewidth modulation (SVPWM) provides enhanced performance for the coupled ten-switch three-phase three-level inverter (TP-TLI). However, it suffers from high common-mode voltage (CMV) and unbalanced neutral-point voltage (NPV). To solve this problem, a CMVR_SVPWM with CMV reduction and NPV control (NPVC) is proposed in this article. By using suitable vectors with lower CMVs and sequences, the amplitude of CMV is suppressed to 50% of the previous strategies for ten-switch TP-TLI. A newly control degree is explored to regular the NPV through the two pairs of newly virtualized vectors in each sector. The dwell time of each selected vector is indirectly calculated to cooperate the NPVC with the CMVR_SVPWM. By enhancing the dwell time of the desired small vector, the NPV can be balanced while maintaining the almost same output quality. The dead-time effect is analyzed, and the resulting CMV spikes is eliminated by increasing the dwell time of the vector which is less than twice the compensation time. It preferentially attempts to eliminated the CMV spikes based on volt-second balance. This minimizes the effect of the proposed compensation method on output quality. A 3-kVA experimental prototype is built up to verify the feasibility and performance of the proposed CMVR_SVPWM.

A Generalized Selective Harmonic Elimination PWM Formulation With Common-Mode Voltage Reduction Ability for Multilevel Converters

In this article, a generalized selective harmonic elimination pulsewidth modulation (SHE-PWM) formulation with common-mode voltage (CMV) reduction ability for multilevel converters (MLCs) is presented. The CMV is suppressed by regulating the low-order dominant zero-sequence harmonics (ZSHs) of the three-phase SHE-PWM waveforms. Two formulations are included in the proposed model to achieve the full range operation objective, i.e., with zero low-order ZSHs in low and medium modulation index (m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> ) range and with an optimal third-harmonic injection in high m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> range. With the proposed formulation, the amplitude of CMV can be effectively reduced for all types of MLCs over the whole m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> range. Besides, two kinds of solving algorithms, i.e., off-line and real-time based, are introduced to provide efficient solution tools targeted at the proposed model. In this article, a case study with three-level neutral-point clamped inverters is discussed in detail to better illustrate the proposed formulation and the coupling effects between the CMV reduction and capacitor voltage balancing objectives of MLCs. Simulation and experimental results based on multiple MLC topologies are carried out to validate the effectiveness of this generalized SHE-PWM formulation with reduced CMV values.

Parallel Operation of Split-Source Inverters for PV Systems: Analysis and Modulation for Circulating Current and EMI Noise Reduction

To satisfy the ever-increasing requirement from load side and improve the power quality through harmonic content reduction, the paralleled converters' structure is seen to be an interesting solution. However, paralleled converters, in which the same dc and ac sides are shared, suffer from a major challenge related to the excessive circulating currents due to the difference in the induced common-mode voltage (CMV) in each converter. This voltage difference is due to the instantaneous potential difference between paralleled phase-legs, due to the discrepancy in circuit and control parameters of paralleled converters. Consequently, zero-sequence circulating current (ZSCC) as well as differential-mode circulating current (DMCC) shall appear between the paralleled converters. In this context, this article utilizes the interleaved pulsewidth modulation (PWM) concept for the ZSCC and DMCC reduction in paralleled split-source inverters (SSIs), where this SSI is a single-stage dc-ac converter and the prior mentioned operation and associated issues have not been investigated yet. This article describes the three-phase SSI structure and its basic operation, and shows the corresponding CMV waveform. Then, based on the shown analysis, an interleaved discontinuous PWM strategy is proposed to restrain the CMV amplitude and reduce the induced circulating currents. Furthermore, the effect of changing the modulation index and interleaving angle on the overall converter behavior has also been evaluated in case of using SSI. The analysis and simulations revealed the effectiveness of the proposed modulation strategy compared to counterparts. Finally, the shown simulation results are validated with an experimental prototype of 1 kW.

H14 Three‐Level Inverter for Common‐Mode Voltage Suppression

This paper presents an H14 three‐level inverter topology and the corresponding control method for common‐mode voltage (CMV) suppression based on the three phase three‐level neutral‐point‐clamped inverter. Operation performance of the proposed H14 three‐level inverter is first analyzed under different switching patterns, and the corresponding CMV under each operation states is investigated. The control method of H14 inverter is presented by following a feasible minimal CMV output within the switching patterns, and the switching function is given which is very easy to be implemented. Furthermore, the operation performances of the proposed H14 inverter in terms of total harmonic distortion of output current, DC link neutral‐point voltage oscillation and CMV are investigated in simulation and hardware‐in‐the‐loop experiment. The verification results show that the proposed H14 three‐level inverter is able to suppress the CMV, the maximum amplitude of CMV is reduced from Vdc/3 to Vdc/6 especially with desirable operation performances of inverter. © 2020 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

Sawtooth Carrier-Based PWM Methods With Common-Mode Voltage Reduction for Symmetrical Multiphase Two-Level Inverters With Odd Phase Number

The increased phase number of multiphase systems enables us to exploit more degrees of freedom, such as the shape of phase carriers in pulsewidth modulation (PWM). The sawtooth carrier-based PWM (SCPWM) techniques are proposed in this article to reduce common-mode voltage (CMV) in both the peak-to-peak amplitude and the changing frequency, and it can be easily extended to symmetrical multiphase two-level inverters with any odd phase number. Theoretical analysis reveals that the switching between mirror-symmetrical carriers within one phase narrows the range of the sum of switching states in all phases, which leads to the reduction of CMV amplitude. Meanwhile, the overlapping of sawtooth carriers' straight edges among different phases slows down the change of the sum of switching states, which results in the decrease of CMV changing frequency. Moreover, the effects of voltage harmonics injection and switches' dead-time settings on the CMV reduction performance under the proposed SCPWM techniques are investigated. Finally, the experiment results in a five-phase induction machine and multiphase RL loads verify the improved CMV performance and the extensibility of the proposed SCPWM methods.

A Generalized Modulation Method for Common-Mode Voltage Reduction of Dual-Input Three-Level Inverter

The dual-input three-level inverter should have the ability to operate in certain areas where the dc-links are unbalanced. This paper proposes a generalized large-medium-zero space vector modulation (GLMZ-SVM) method to obtain high-quality output currents and suppress common-mode voltage (CMV) amplitude simultaneously when the dc-links are unbalanced. In this method, a modified space voltage vector diagram (MSVVD) based on the unbalancing factor is obtained, which is highly asymmetrical compared to the space vector diagram when the dc-links are balanced. Then, a novel sector division method of MSVVD is presented by six medium vectors and six large vectors. In each sector, the large, medium, and zero vectors are used to synthesize the reference voltage vector to reduce the CMV amplitude. The duty cycles of large, medium and zero vectors are calculated based on the modified volt-second balance principle with the unbalancing factor. To further reduce harmonics and avoid switching losses between switching cycles, a symmetrical five-segment switching sequence is designed. Comparisons with conventional methods show that the CMV amplitude of the proposed method is reduced by half and the high-quality output currents are obtained. Both simulation and experimental results validate the correctness of the theoretical analyses and the effectiveness of the proposed scheme.

A Novel Low Common-Mode Voltage Modulation Strategy for ANPC-5L Inverter

In order to suppress the leakage current of the active neutral point clamed five-level (ANPC-5L) inverter, this paper proposes a novel low common-mode voltage (CMV) modulation strategy based on the space vector modulation thought. Only the 55 voltage vectors with low CMV amplitude instead of all 125 voltage vectors are utilized. The CMV amplitude is suppressed to one-twelfth of the DC bus voltage (Vdc). In the simplified five-level space vector diagram, “obtuse triangle” synthesis principle is used to control the CMV changes twice in each carrier cycle, and get lower output current total harmonic distortion (THD). According to the vector thought, a carrier implementation method based on zero sequence voltage injection and carrier splitting is proposed. This method simplifies the calculation and is easy to implement.Simulation results prove the correctness and feasibility of this low CMV modulation strategy.

Improved Synchronized Space Vector PWM Strategy for Three-Level Inverter at Low Modulation Index

Aimed at reducing the switching loss and common-mode voltage amplitude of high-power medium-voltage three-level inverter under low modulation index conditions, an improved synchronous space vector PWM strategy is proposed in this paper. The switching times in each fundamental period are reduced by the re-division of small regions and the full use of the redundant switching state. The sum of switching algebra is introduced as an evaluation index and the switching state with the minimum value of the sum of switching algebra are adopted. Then, the common mode voltage amplitude is reduced. The theoretical analysis and experimental results show that the improved modulation strategy proposed in this paper can effectively reduce the switching loss and common-mode voltage amplitude of the inverter under the condition of the low modulation index. Moreover, the neutral-point voltage ripple is also reduced simultaneously.

Hybrid SVPWM Scheme to Minimize the Common-Mode Voltage Frequency and Amplitude in Voltage Source Inverter Drives

In this paper, a hybrid space vector pulsewidth modulation synthesis is proposed to lower the frequency and amplitude of the common-mode voltage (CMV). The conventional space vector pulsewidth modulation (SVPWM) techniques for inverters generate a high-frequency CMV. The CMV causes significant bearing current flowing through the path to the ground and leads to premature bearing failure, especially in high switching frequency drive systems. Furthermore, previously proposed CMV reduction studies focus on the reduction of CMV amplitude, leaving a high-frequency CMV. The proposed control algorithm divides each sector in the space vector hexagon into three segments based on the modulation index and the angle of the reference voltage vector. In each segment, the space vectors that produce minimal CMV are selected to synthesize the reference voltage vector. A fair comparison with the conventional CMV reduction methods is made by comparing the CMV characteristics, harmonic distortion factor, dc current ripple, and the switching losses for each method. Both simulation and experimental results have validated the effectiveness of the proposed approach.

Common Mode Voltage Reduction of Single-Phase Quasi-Z-Source Inverter-Based Photovoltaic System

A common mode voltage (CMV) reduction method is proposed for the active power filter (APF) integrated single-phase quasi-Z-source inverter (qZSI) based photovoltaic (PV) power system. The APF integrated qZSI completely compensates the dc-side double-line-frequency (2ω) ripple through the APF capacitor, while maintaining low qZS inductance and capacitance. The proposed method reduces the CMV amplitude to half of that using the traditional sinusoidal pulse width modulation (SPWM). The switching and conduction power losses are analyzed. Simulation and experimental results demonstrate the proposed method reduces CMV without comprising performance and efficiency of the APF integrated single-phase qZSI.

A Sawtooth Carrier-Based PWM for Asymmetrical Six-Phase Inverters With Improved Common-Mode Voltage Performance

A sawtooth carrier-based sinusoidal pulse width modulation (SC-SPWM) technique for asymmetrical six-phase two-level inverters is proposed in this paper, which could reduce both the peak-to-peak amplitude and the changing frequency of the common-mode voltage (CMV). The intersection-plotting method reveals that the mirror symmetrical sawtooth carriers for two three-phase groups can help optimize the distribution of overlapping areas, which is the CMV reduction mechanism of SC-SPWM. Additionally, the Fourier analysis is employed to quantitatively evaluate the modulation index and harmonic performance of SC-SPWM compared with the conventional SPWM and two phase-shifted SPWM methods. Also, further analysis demonstrates that dead time does not affect the reduction of CMV in a noticeable way. Finally, both simulation and experimental results coincide with the theoretical analysis that the proposed SC-SPWM shows the best performance in reducing the CMV amplitude and changing frequency among these four SPWM methods, though it leads to a higher phase current distortion.

A Double Modulation Wave CBPWM Strategy Providing Neutral-Point Voltage Oscillation Elimination and CMV Reduction for Three-Level NPC Inverters

This paper proposes a double modulation wave carrier-based pulse width modulation (CBPWM) strategy for the three-level neutral-point-clamped (NPC) inverter. This modulation strategy not only overcomes one of the main problems of the NPC inverter, which is the low-frequency voltage oscillation on the neutral point, but also reduces the common-mode voltage (CMV) generated by the inverter. Through the rigorous theoretical derivation, the unified duty cycles of each phase are derived, and the double modulation waves can be easily obtained according to different optimization objectives. However, in the previous double wave CBPWM work, the modulation strategy could not reduce the CMV, whose amplitude is still the same as that of the conventional CBPWM strategy. By rearranging the switching sequence, the vectors corresponding to the large CMV amplitude have been eliminated, and the amplitude of CMV can be reduced by half. Considering the occurrence of neutral-point voltage perturbations, a voltage controller is adopted to recover from the imbalance. Finally, the performance of the proposed modulation technique is verified by the experimental results.

Stator inter‐turn fault detection in closed‐loop controlled drive based on switching sideband harmonics in CMV

This study proposes a method for stator fault detection of inverter-fed induction machine in closed-loop control. The sideband response of inverter switching harmonics in common-mode voltage (CMV) is employed to detect the stator inter-turn fault, thus no additional injected signal is necessary. However, the PWM nature harmonics introduce undesired CMV signals, depending on the inherent imbalance or resistance asymmetry. For this reason, the CMV amplitude is not suitable to indicate the fault directly. In this study, the behaviour of switching harmonic is analysed first, and then a simple but efficient stator fault model is demonstrated. To suppress the adverse interference from inverter, an inter-turn fault indicator is proposed by utilising both of the switching sidebands. This method can obtain fault location and severity with low sensitivity to steady operating condition and stator imbalance. The experimental results validate the effectiveness of the proposed method.

PWM Impact on CM Noise and AC CM Choke for Variable-Speed Motor Drives

This paper analyzes pulsewidth modulation (PWM) methods' impact on the motor drives' common-mode (CM) noise current and CM choke saturation. The modulation in the motor drive terminals serves as the CM noise source. A few improved PWM methods could reduce the CM voltage amplitude in comparison with the conventional space vector PWM and discontinuous PWM. However, some harmonics of the improved PWM methods increase when considering the spectrum. Because the CM loop of the motor drive system is an L-R-C circuit which has its resonant frequency, the CM noise current is highly influenced by the noise near the resonant frequency. This paper studies the CM current with different PWM methods and claims that the design of PWM methods and switching frequency should be together with the CM loop impedance. Reduced CM voltage does not mean reduced CM current. With a CM choke to attenuate the CM noise, the choke size is determined by the CM volt-seconds on the choke. This paper studies the general case and the worst case of the choke size. The conclusions are supported by simulation and experimental results.