Amplitude-locked Loop Research Articles

A 170 MHz to 330 MHz Wideband 90 nm CMOS RC–CR Phase Shifter with Integrated On-Line Amplitude Locked Loop Calibration for Hartley Image Rejection Transceiver

A 160 MHz bandwidth 90° active RC–CR phase shifter with integrated on-line amplitude locked loop (ALL) calibration targeted to 802.11ac 5 GHz wireless local area network (WLAN) applications is presented in this paper. The quadrature phase shifter is a key component for transceivers employing the Hartley image rejection architecture. The passive RC–CR phase shifter generates the required two quadrature outputs with an accurate 90° phase shift over the required bandwidth but lack the required accuracy in amplitude matching. A 90 nm CMOS microelectronic implementation of an RC–CR phase shifter is proposed with active resistors that are adjusted by an integrated on-line ALL calibration system to maintain matching amplitudes of the quadrature outputs over the required bandwidth. The on-line ALL calibration system employs peak detectors, comparators, digital logic control, and charge pump to incrementally adjust the active resistors while converging to matched amplitudes similar to the operation of phase-locked loop with a phase-frequency detector and charge pump. The resulting 90 nm implementation supports − 40db to − 70db image rejection ratios (IMMRs) over the IF 170 MHz to 330 MHz bandwidth. The 90 nm CMOS implementation is fully functional considering process variations based on 200 Monte Carlo simulations.

A Wideband Low-Power LC-DCO-Based Complex Dielectric Spectroscopy System in 0.18- $\mu \text{m}$ CMOS

A low-power integrated LC -oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity $\varepsilon _{r}^{\prime }$ is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter. The imaginary relative permittivity $\varepsilon _{r}^{\prime \prime }$ increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop is used to fix the amplitude and linearize the relation between the oscillator bias current and $\varepsilon _{r}^{\prime \prime }$ . The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling is used to mitigate the impact of flicker noise, temperature variations, and frequency drifts. A prototype is implemented in 0.18- $\mu \text{m}$ CMOS process with a total chip area of 6.24 mm2 to operate in 1–6-GHz range using three dual bands LC oscillators. The total power consumption ranges from 10 to 24 mW depending on the operating frequency. The sensor measures complex permittivity within 2% accuracy for the real part $\varepsilon _{r}^{\prime }$ and 5% for the imaginary part $\varepsilon _{r}^{\prime \prime }$ . The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading.

A Wide-Band Fully-Integrated CMOS Ring-Oscillator PLL-Based Complex Dielectric Spectroscopy System

A fully-integrated sensing system is proposed for wideband complex dielectric detection of materials under test (MUT). The system utilizes a ring oscillator-based phase-locked loop (PLL) for wide tuning range and precise control of the sensor's excitation frequency. Characterization of both real and imaginary MUT permittivity is achieved by measuring the frequency difference between two voltage-controlled oscillators (VCOs): a sensing oscillator, with a frequency that varies with MUT-induced changes in capacitance and conductance of a delay-cells' sensing capacitor loads, and a MUT-insensitive reference oscillator that is controlled by an amplitude-locked loop (ALL). The fully integrated system is fabricated in 0.18 $\mu{\rm m}$ CMOS, and occupies 6.25 ${\rm mm}^{2}$ area. When tested with common organic chemicals $(\epsilon_{r}^{\prime} , the system operates between 0.7–6 GHz and achieves 3.7% maximum permittivity error. Characterization is also performed with higher $\epsilon_{r}^{\prime}$ water-methanol mixtures and phosphate buffered saline (PBS) solutions, with 5.4% maximum permittivity error achieved over a 0.7–4.77 GHz range.

Design and Application of Amplitude-Locked Loop Separation System Based on SignalWAVe

In this paper, we adopt concepts from the SignalWAVe development platform for the multi-speech signal separation system of a frequency modulation system. The signal separation system is formed using a phase-locked loop in combination with an amplitude-locked loop (ALL) and is modeled using a digital finite-impulse response (FIR) filtering algorithm. Therein, the objective is to improve the signal distortion of co-channel interferences and additive white Gaussian noise (AWGN). In comparison to a traditional separation system, the ALL is achieved in the monitored system and in signal interception applications with a characteristic analysis based on the power spectrum density. The field programmable gate array (FPGA) design platform has the advantages of flow simplicity, easy reconfiguration, and high compatibility for verification. The design system is operated in real time and is implemented in the system model using various chip designs. The FPGA is implemented system as a system on a chip for high efficiency. According to the simulated performances under an applied AWGN channel, the ALL system in combination with a digital FIR filter achieves prefect performance. The SignalWAVe verification system was also implemented on the chip by building, verifying programs, and implemented communication functions for practical application in the industry.

Amplitude-locked loop analysis for calibration applications

A linear analysis of an ALL, as it would be used in an amplitude calibration, is presented. The impact of different loop filter choices is considered, for steady-state error and loop dynamics as well as for disturbances in the input amplitude and peak detector ripple. It is shown that in most applications a loop filter with an integrator is desirable.

Improvement of FM demodulator with cochannel FM interference

Originally, frequency modulation (FM) was conceived to minimise the effect of additive noise, since additive noise is the principal source of signal corruption in amplitude modulation (AM), the pre-cursor of frequency modulation. When the FM signal is received, the additive noise is removed by the action of a limiter. This process is a necessary part of FM demodulation. There are a number of ways to recover the modulating signal from the FM signal to improve cochannel interference (CCI). Without hard limiting, the signal is corrupted by both phase noise and by amplitude noise. It had not been possible to achieve FM demodulation without first using a hard limiter, not until the realisation of the amplitude-locked loop (ALL).

Co-channel FM interference suppressed by using the amplitude-locked loop for digital communication

An amplitude-locked loop (ALL) is a high-gain, high-bandwidth servo-loop similar to a phase-locked loop (PLL) but operating in the amplitude domain rather than the frequency domain. The ALL has been used in combination with a PLL (the FM 201/5) and some additional circuitry to achieve a major improvement in frequency modulation technology. This includes co-channel interference (CCI), multipath interference and threshold extension . This work is the natural extension of this approach to digital communication systems.

Application of a PLL and ALL noise reduction process in optical sensing systems

A novel approach to the demodulation of a frequency modulated optical signal using an amplitude-locked loop (ALL) in the presence of noise is presented. The ALL is the mathematical dual of the phase-locked loop (PLL), but works on amplitude rather than phase. This technique will benefit areas where noise due to scattering or multiple reflections is present.

Analysis of an amplitude-locked loop

The amplitude-locked loop (ALL) is a closed-loop servosystem which is the dual of the phaselocked loop (PLL). An analysis is obtained which shows that the circuit has an output which is the reciprocal of the modulus of any carrier-based input and can be made to be phase-sensitive.

On-chip automatic tuning based on amplitude detection and its application in CMOS continuous-time filters

This paper describes the results of investigation of a continuous-time CMOS voltage controlled IC filter using amplitude detectors in the tuning scheme in the form of an amplitude-locked loop. This tuning scheme is used to stabilize the filter characteristics. A prototype 20-kHz fifth-order Chebyshev low-pass filter with 0.1-dB passband ripple was realized to study the performance of the tuning scheme. Voltage controlled integrators were used as building blocks, and the design details of these integrators, whose unity-gain frequency can be varied from 8 to 32 kHz are given. Two amplitude detector circuits—a precision rectifier and an averaging rectifier-were used to test the tuning scheme. The filter cutoff frequency was held within 1% of its room temperature value over the temperature range of 0° to 70°C. All the circuits were fabricated in a standard 3-micron double-metal p-well CMOS process.