Amplitude Control Loop Research Articles

Notice of Violation of IEEE Publication Principles: A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit

A multi-rate 9.953-12.5-GHz low phase noise LC oscillator was realized in a 90-GHz f/sub T/ 0.2 μm SiGe BiCMOS process. It achieves a 36% tuning range by combining a 35% open-loop frequency calibration range having a sub-0.1% residual error with a 1% closed-loop varactor frequency tuning. The oscillator gain is below 130 MHz/V, while having less than 10% variation over the entire tuning range. The varactor is realized with multiple parallel-connected cells consisting of constant capacitors and voltage-controlled resistors that bring a lower process variation and a higher quality factor in comparison with standard diode and MOS varactors. A dual regulator architecture was used to provide both high PSRR and low output voltage noise. The supply pushing was reduced below 100 kHz/V by using a pushing cancellation circuit that balances the negative and positive voltage coefficients of the different nonlinear capacitors connected to the LC tank. A discrete-time automatic amplitude control loop using a variable tail resistor architecture was implemented to optimize the VCO's phase noise performance. The VCO specifications include 9.953-12.5-GHz frequency range, 0.1% frequency calibration error, -122 dBc/Hz phase noise at 1 MHz offset, <3 kHz 1/f/sup 3/ corner frequency, <-80 dBc spurious tones, 250×400 μm/sup 2/ die area and 5-mA bias current from a 3.3-V supply.

Cascaded integrator comb filters with smoothly varying coefficients for reduced delay in synchrotron feedback loops

The Rapid Cycling Synchrotron (RCS) of the J-PARC complex in Tokai, Japan, is designed to accelerate a high intensity proton beam from 181 MeV, and later 400 MeV to 3 GeV in 20 ms within the 40 ms machine cycle. The beam power up to 1 MW demands a stable beam control to avoid excessive losses and activation of the accelerator chain. The fully digital control system is based on quadrature modulation and demodulation. In the amplitude control loops standard FIR filters separate the harmonics (h � 2) and (h � 4) after down conversion. For the phase loops at (h � 2) and (h � 4), intended to damp synchrotron oscillations, the delay in a FIR filter would limit the loop stability. Cascaded integrator comb filters, also called CIC filters, provide a shorter delay because they filter the longitudinal beam signal only where it is necessary. The notches are located at multiples of the revolution frequency of the proton beam. For fixed frequency accelerator applications, digital comb filters with fixed clock frequency are widely used to improve loop stability. For variable frequency accelerator applications, as in a proton synchrotron, where the frequency swing is larger than the notch width, usually the clock frequency of the comb filter is variable and chosen to be an integer multiple of the particle revolution frequency. At J-PARC RCS, the clock frequency has to be fixed. Tracking the frequency would require a variable noninteger number of filter taps. Here we present a filter, based on the weighted output of 2 CIC filters with variable length, and one tap difference. The filter function looks like a CIC with smoothly varying coefficients, where the notches follow the revolution frequency of the proton beam. The delay of this filter is approximately half of the corresponding FIR filter, so that the phase loops have a higher stability margin.

An analog GFSK modulator in 0.35-/spl mu/m CMOS

An analog Gaussian frequency shift keying (GFSK) modulator designed in 0.35-/spl mu/m CMOS consumes 600 /spl mu/A from a 3-V supply and realizes an analog implementation of the FM differential equation. The modulator operates at baseband and is intended for use in a direct-conversion Bluetooth transmitter. It achieves a frequency deviation of 160 kHz with better than /spl plusmn/3% accuracy. The modulator implements an amplitude control loop to achieve a well-defined output swing. The total output harmonic distortion is less than 1%.

A Precise 90&amp;lt;tex&amp;gt;$^circ$&amp;lt;/tex&amp;gt;Quadrature OTA-C Oscillator Tunable in the 50–130-MHz Range

We present a very-large-scale integration continuous-time sinusoidal operational transconductance amplifiers quadrature oscillator fabricated in a standard double-poly 0.8-/spl mu/m CMOS process. The oscillator is tunable in the frequency range from 50 to 130 MHz. The two phases produced by the oscillator show a low-quadrature phase error. A novel current-mode amplitude control scheme is developed that allows for very small amplitudes. Stability of the amplitude control loop is studied as well as design considerations for its optimization. Experimental results are provided.

A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop

The automatic amplitude control (AAC) loop is an indispensable element for the practical realization of VCOs embedded in a complete transceiver. Its noise however can unacceptably degrade the single-sideband-to-carrier ratio (SSCR) performance of the oscillator, this problem being even exacerbated in low-voltage circuits. This paper addresses the design issues of a low-voltage low-noise differential LC-VCO with AAC, tunable within a 2.3-2.8-GHz frequency range, fully integrated in bipolar technology with 2-V power supply. First, the mechanisms through which the AAC noise affects the output phase are identified as the poor indirect stability and the AM-to-PM conversion due to the varactors. The effect of the AAC noise is discussed and substantially reduced with suitable design choices. We show that the achievable noise-to-signal ratio is bounded by the shot noise coming from the bias source of the differential oscillator, an intrinsic limit set by the low supply voltage which does not allow for degeneration of the tail transistor. Second, the design of the AAC is discussed. A large gain-bandwidth product (GBWP), about 100 MHz, has been implemented in order to correct for the fast oscillation amplitude variations and reduce the effect of the ground line disturbances. The expected value of the phase noise level, SSCR at 100 kHz =-104 dBc/Hz, is tightly matched by the experimental results. The core oscillator dissipates 7 mA, while less than 600 /spl mu/A are drawn by the AAC circuit.

A universal 0.03-mm/sup 2/ one-pin crystal oscillator in CMOS

A one-pin crystal oscillator with an integrated load capacitance of 15 pF has been realized in a standard 0.35-/spl mu/m CMOS technology. Due to the structure of the oscillator and the use of MOS gate capacitance for the load capacitors, the chip area can be very small. The total active area including load capacitors is less than 0.03 mm/sup 2/. The design can be operated with supply voltages in the range of 1.4-3.6 V and allows crystal frequencies in the range of 3-30 MHz. The current consumption of the oscillator core is 180 /spl mu/A at 10 MHz with 3.3-V power supply. It produces a rail-to-rail output swing, regulated by an amplitude control loop, and has the same flexibility and ease of frequency tuning as a common Pierce oscillator. As no special IC process options are required, the design is very suitable for clock generation in digital very-large-scale-integration chips.

Non-linear Control of the Oscillation Amplitude of a Coriolis Mass-Flow Meter

In a Coriolis mass-flow meter (CMFM) the process fluid (of potentially variable density) flows through a pipe undergoing yawing vibration to generate the required transverse Coriolis acceleration. Reliable control of the amplitude of vibration is necessary for this and other applications employing a deliberately oscillating mass-spring-damper where the mass and damping are subject to variation. The method proposed uses positive feedback of the output velocity to cancel the internal damping, with a gain determined by an outer sampled-data amplitude-control loop. The insertion of two non-linearities into the outer loop is shown to induce overall global linearity. Hence a straightforward proportional-plusintegral control design procedure gives results which are uniformly satisfactory over desired amplitudes spanning several decades, unlike naive methods which are effective for only a limited range of amplitudes. A simple desaturation strategy overcomes potential problems caused by power limits in the actuator. A practical example of successful use of the overall controller on a CMFM indicates the improvement over an existing analogue design.