DC Gain Of Amplifier Research Articles

Calibration of Cyclic-Pipelined ADCs Using CMOS for Area-Efficiency

One of the principal obstacles in the development of pipeline analog-to-digital converters (ADCs) is the imprecision associated with residue amplification. Operational amplifiers (Op-Amps) that possess high gain and speed are recognized for their excessive power consumption, making them unsuitable for employment in proficient analog-to-digital converters (ADCs). The study presents a new method for foreground calibration that addresses amplification differences in cyclic-pipelined ADCs, reducing the need for internal amplifier DC gain. The calibration technique was applied to a cyclic-pipelined ADC with a sampling rate of 2 MS/s and 16-bit resolution. The design of this ADC was optimized for area efficiency, and its fabrication utilized 180 nm CMOS technology. The analog-to-digital converter (ADC) used a 5-bit resolution sub-ADC performing 4 cycles to reduce potential errors. Each cycle contained one bit of redundancy. A fixed-point iterative algorithm was used to find the exact gain for each amplifier. Simulation data shows a SINAD of 100. 6 dB, despite a 57 dB DC gain amplifier. The ADC's active area is 1. 8 mm2 at 30 consumption. 43 mW.

Research on the Polygraph: the CMOS Neural Amplifier

The polygraph is an effective piece of equipment to detect if the suspect is lying in order to track down the criminal. The paper simulates and sets up the host part of the polygraph in order to explain how the polygraph works and some fields to use it. And we successfully make a neural amplifier to show the way that the host amplifies neural signals, and has a low passband that can filter out high-frequency signals. The circuit has two parts the folded cascode amplifier DC gain is 64.56, the -3dB bandwidth is about 100kHz and the total current consumption is 4uA and the capacitive feedback amplifier passband gain is 40dB and the passband is from about 3Hz to 5kHz. It is of great value not only in the field of criminal investigation, but also in VR, artificial intelligence (AI), and mental health. Because it can record and let people observe human brain activity and emotional changes. What’s more, with its development of it, it can solve many small crimes automatically, which means police can have more time and energy to deal with difficult cases and society can be more stable.

Macro Model for Discrete-Time Sigma‒Delta Modulators

This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed macro model is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As such, since the macro model is a true representation of the actual transistor level circuit, a moderately good accuracy can be obtained. In addition, the proposed macro model includes the major amplifier, comparator, and switch‒capacitor non-idealities of the sigma‒delta modulator such as amplifier DC gain, GBW, slewrate, comparator bandwidth, hysteresis, parasitic capacitance, and switch-on resistance. The results show the simulation time of the proposed macro model sigma‒delta modulator is only 6.43% of the transistor level circuit with comparable accuracy. As a result, the proposed macro model can facilitate the circuit design and leverage non-ideality analysis of discrete-time sigma‒delta modulators. As a practical design example, a second order discrete-time sigma‒delta modulator with a five-level quantizer is realized using the propose macro model for GSM and WCDMA applications.

Experimental implementation of a 14 bit 80 kSPS non-binary cyclic ADC

This paper presents a prototype of 14 bit 80 kSPS non-binary cyclic ADC without high accuracy analog components and complicated digital calibration. Since the redundancy of non-binary ADC tolerates the non-idealities of analog components such as capacitor mismatch and finite amplifier DC gain, the design consideration of this high accuracy ADC can be only focused on the capacitance of sampling capacitor to satisfy the overall kT/C noise target, the drivability and linearity of amplifier without any high accuracy analog components. The proposed proof-of-concept cyclic ADC has been designed and fabricated in TSMC 90 nm CMOS technology. Measured SNDR = 81.9 dB is achieved at Fs = 80 kSPS with a simple radix-value estimation technique. No other complicated digital calibration is used to compensate the non-linearity of ADC caused by MOM capacitors and a poor gain of the amplifier as low as 66 dB. Measured DNL is − 0.6/+ 0.67 LSB and INL is − 1.2/+ 1.6 LSB. Prototype ADC dissipates 8mW at supply voltage is 3.3 V in analog circuits.

Robust Cyclic ADC Architecture Based on <i>β</i>-Expansion

In this paper, a robust cyclic ADC architecture with βencoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs β-expansion code and has an advantage of error correction. This feature makes ADC robust against the offset of comparator capacitor mismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because the power penalty of high-gain wideband amplifier and the required accuracy of circuit elements for high resolution ADC can be relaxed, the proposed architecture is suitable for deep submicron CMOS technologies beyond 90 nm. We also propose a β-value estimation algorithm to realize high accuracy ADC based on β-expansion. The simulation results show the effectiveness of proposed architecture and robustness of β-encoder. key words: robust ADC, β-expansion, redundancy, cyclic ADC, radixvalue estimation algorithm

Trade off between polysilicon film quality and thin film transistor operational amplifier DC gain

We have fabricated thin film transistor operational amplifiers on a variety of polycrystalline silicon films. We have examined the open loop DC gain of these modules, and have observed that higher quality polycrystalline silicon films usually cause a negative impact on the DC gain of the amplifier. In this paper we have attempted to quantify this relationship, presenting the gain as a function of the transistor mobility, threshold voltage and channel length modulation parameter, which collectively can describe the quality of the active film. We have found that primarily the saturation characteristics of the transistor, as represented by the channel length modulation parameter, and the device threshold voltage have the biggest impact on amplifier gain.

Design techniques for switched-capacitor broad-band phase-splitting networks

A phase-splitting network is another type of circuit that is suitable to be integrated using the switched-capacitor (SC) technique. However, using existing all-pass SC configurations to realize such networks results in excessive capacitance spread because phase-splitting networks have very low real poles under a wide signal frequency band. Simple analytical expressions derived in this paper show that combining first-order sections of such networks into low- Q biquads does not reduce the capacitance spread unless the dynamic range of the filter can be sacrificed. A new biquad configuration is proposed for capacitor area efficient realization of low pole all-pass filters. The biquad combines a T -cell with a conventional integrator. The T -cell integrator realizes the low pole with a product of two capacitance ratios instead of a single capacitance ratio to reduce the capacitance spread. A simple and systematic design procedure is presented for the determination of capacitance values as a function of the poles to be realized. The design procedure achieves minimum total capacitance and equal dynamic range for all amplifiers simultaneously. Commonly performed rescaling of capacitance values after computer simulation is not necessary. The new biquad attenuates offset and flicker noise. However, finite amplifier dc gain and white noise have greater influence on the filter performance. Analytical expressions for transfer function deviations are derived which indicate the amplifier dc gain necessary for a given \omega_0 tolerance. Computer simulations show that the total integrated noise of the T -cell biquad only slightly increases compared to that of the conventional biquad realizing the same function. A design example is given which illustrates the design procedure. Compared to the realization of the same transfer function with conventional biquads, T -cell realization reduces the total capacitor area by almost a factor of 20.

Switched-capacitor ladder filters with offset-insensitive time-continuous feedback integrators

The possibilities of designing high-order switched-capacitor (SC) ladder filters which are insensitive to the DC offset voltage and at the same time guarantee that all operational amplifiers operate permanently in their active region are investigated. The proposed circuit technique is based on an offset-insensitive fully differential topology, where all operational amplifiers are maintained in the active region by time continuous feedback capacitors. The damping introduced by these additional capacitors leads to a lossy SC ladder filter. A comparative example between a lossless and a lossy 5th-order allpole ladder filter is given in terms of Monte-Carlo sensitivity simulation, showing how the suggested technique can show similar performances. The effect of the finite operational amplifier DC gain on the frequency response of the lossy SC ladder filters can be compensated by the use of a simple predistortion method. The technique seems to be attractive for GaAs technology, where real operational amplifiers can put serious limitations on monolithic analogue designs.

A novel second-order canonical RC-active realization of high-pass notch filter

A high-pass notch filter with variable gain greater than unity is realized using a differential amplifier and only two capacitors that can be equal. The transmission zero and pole frequency are completely independent of the amplifier dc gain. Design formulas, sensitivity analysis, and measure and trim tuning process are presented. An example of a 60-Hz rejection filter is discussed, the response of which is within the required specifications even with a \pm 5-percent capacitance variation. Two modifications of the original structure can be used to realize the same filter, extending the available range of the gain to cover all requirements.