Amplifier Offset Voltage Research Articles

A 17.6-Bit 800-SPS Energy-Efficient Read-Out IC With Input Impedance Boosting

A 17.6-bit, 800-sample-per-second (SPS) read-out integrated circuit has been implemented for a bridge sensor. The read-out integrated circuit has a capacitively-coupled instrumentation amplifier (CCIA) with a sensor offset voltage compensation circuit, an amplifier offset voltage compensation circuit, and an input impedance boosting loop (IBL). Followed by the CCIA, a programmable-gain third-order discrete-time incremental delta-sigma (ΔΣ) analog-to-digital converter (ADC) with an output data-rate of 12.8 kHz shortens the sensing time to reduce the static power consumption of the resistive bridge sensor and the read-out IC. To boost the input impedance of the CCIA, the system-level input and output choppers operate at a frequency of 12.8 kHz. The ΔΣ modulator converts the modulated signal to digital with a sampling clock of 4 MHz. The system-level chopping reduces the residual offset and the low-frequency noise with an on-chip cascade of integrators (CoI) filter. Implemented in a 0.13 μm CMOS process, the read-out circuit achieves an input impedance of 22 MΩ at a data-rate of 800 SPS, a sensor offset compensation range of ± 350 mV, a maximum effective resolution of 17.6 bits, and an input-referred noise of 1.72 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> at a gain of 128. It draws an average current of 106.3 μA from a 3 V supply and 1.3 μA from a 1.5 V supply.

A non-pipelined ADC with a GM-R amplifier

A GM-R amplifier is proposed as a residual amplifier to implement a 16-bit two-stage non-pipelined ADC in intermittent signal acquisition applications. Unlike common capacitive feedback amplifiers, residual amplifiers utilize resistor ratios to generate constant gain for small input amplitude ranges and wide temperature ranges. The input circuit of the proposed amplifier consists of two source followers and a bridge resistor, thus converting residual voltages to currents, and the transconductance is the reciprocal of the bridge resistor. The amplifier offset voltage is corrected by a one-time foreground offset calibration, and the gain error is calibrated with the capacitor weights in the first stage. Redundancy is adopted between the two stages to accommodate the residual offset voltage after calibrating the offset voltage of a comparator and the gain variation. A design prototype is implemented in 180 nm CMOS technology, occupies a 0.69 mm2 footprint, and consumes 3.0 mW from 1.8/5 V power supplies. After calibration, it achieves the SNR of 88.2 dB, SNDR of 87.6 dB, and THD of −95.6 dB at 200 kHz sampling rate. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.62/+0.74 LSB and −1.39/+1.50 LSB, respectively.

Dynamic Zero Current Method to Reduce Measurement Error in Low Value Resistive Sensor Array for Wearable Electronics.

One advantage of a resistive sensor array (RSA) with shared rows (M) and shared columns (N) is the reduced number of wires from M × N + 1 to M + N which can greatly lessen the complexity and burden on wearable electronic systems. However, the drawback is the crosstalk current effect between adjacent elements, which will lead to high measurement error. Although several solutions have been reported, they mainly focus on RSAs with high resistance (≥100 Ω). There is a lack of research that addresses RSAs with resistor values below 100 Ω. Here, we introduce a new circuit design named the dynamic zero current method (DZCM) to further decrease the measurement error. From the low value RSA test with ideal resistors, the DZCM exhibits lower error than the zero potential method (ZPM). In the case of the error variation ratio of amplifier offset voltage, the DZCM has a 4%/mV (row) to 7%/mV (column) ratio, while the ZPM has an almost 25%/mV (row) to 45%/mV (column) ratio and it increases with array size.

Sub-1-V BGR and POR Hybrid Circuit With 2.25-μA Current Dissipation and Low Complexity

Based on three groups of different offset voltages, a bandgap reference (BGR) and power-ON reset (POR) hybrid circuit is implemented in 65-nm CMOS. The BGR using amplifier offset voltage and current matching, and the POR using offset voltage comparison and loop settling feature, respectively, are proposed. This circuit, with low-quiescent current, not only generates a stable reference voltage independent of voltage and temperature variations, but also provides a high-robust supply-ramp-rate-tolerant power-ON/brown-out reset signal with a hysteretic window of 18–24 mV. Experimental results show that the circuit with line regulations (LNRs) of 2.63%–4.28%/V and temperature coefficients (TCs) of 22–32 ppm/°C across multiple chips has a power dissipation around $2.25~\mu \text{W}$ from a 1-V supply voltage. The circuit achieves a low noise density of 18.5 nV/ $\surd $ Hz at 100-Hz offset frequency and a good figure of merit (FoM) performance. With an active core area of 0.014 mm2, the circuit has fixed reset trip voltages under the supply ramp time of 0.4–100 ms.

Sense amplifier offset voltage analysis for both time-zero and time-dependent variability

This paper presents an accurate technique to extensively analyze the impact of time-zero (i.e., global and local variation) and time-dependent (i.e., voltage, temperature, workload, and aging) variation on the offset voltage specification of a memory sense amplifier design using 45 nm predictive technology model (PTM) high performance library. The results show that increasing the supply voltage both for time-zero and time-dependent reduces the offset voltage specification marginally, irrespective of the process corners. In contrast, the offset voltage specification is very sensitive to the temperature and the workload, i.e., the applied voltage patterns. The results also show that a balanced workload results in a significantly lower offset voltage specification. The above results can be used to estimate the required offset voltage accurately for a given lifetime, and operational conditions such as workload, temperature, and voltage; hence, enable the designer to take appropriate measures for a high quality, robust, optimal and reliable design.

Low‐complexity 0.55‐V 2.5‐μW bandgap reference and power‐on reset hybrid circuit

A near-threshold low-complexity bandgap reference (BGR) and power-on reset (POR) hybrid circuit is implemented in 65 nm CMOS, with an ultra-low supply voltage of 0.55 V and power consumption of 2.5 μW. The BGR employing amplifier offset voltage and current matching, and the POR based on offset voltage matching and loop settling feature, are proposed. The circuit-level simulation results verify that the presented implementation, not only generates a stable reference voltage with the typical temperature coefficient of 120 ppm/°C and line-regulation feature of 3.3%/V, but provides a robust reset signal with power-on and brown-out detection function. The proposed near-threshold circuit has ultra-low power supply and design complexity, both for BGR and POR modules, when compared to the reported.

Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory

We prove analytically that the yield of static random access memory (SRAM) is intrinsically a function of its architecture owing to the correlation among cell failures. In addition, architecture-aware analytical yield models are proposed for read access. The yield results using the proposed models show that the most dominant factor determining yield is the variation in the voltage difference between bitlines due to the cell leakage current variation according to the SRAM architecture. The models also show the possibility that the most dominant factor determining the yield can change with the relative ratios among the amounts of changes in the correlation, recovery sample space, distributions of the sense amplifier enable time, voltage difference between bitlines, as well as sense amplifier offset voltage, memory capacity, and redundancy scheme. The proposed yield models show that combined row and column redundancy ensures the highest yield, whereas column redundancy is the most efficient.

Resistorless switched‐capacitor bandgap voltage reference with low sensitivity to process variations

A novel switched-capacitor bandgap voltage reference circuit is presented that dispenses entirely with the use of resistors. Since capacitors are used instead of resistors, variability problems from devices mismatch and process spread are reduced, compared with traditional topologies. The proportional-to-absolute-temperature drift and the complementary-to-absolute-temperature drift voltages are both generated by the same PNP vertical bipolar transistor obtained in bulk CMOS, minimising mismatch problems even further. A switched-capacitor circuit stores, amplifies and sums these voltages, generating the bandgap voltage after five clock cycles. The operational amplifier offset voltage is also cancelled by the switching scheme proposed. The current sources which are used to generate different junction current densities are averaged in the switching process, reducing their mismatch impact on the circuit performance. A systematic comparison to a traditional bandgap topology with resistors is presented, both designed in the CMOS 180 nm process, and demonstrates the better performance of the new topology with respect to the former. Monte Carlo simulations show significantly lower spread resulting from devices mismatch in the output reference voltage (VREF) and also in its temperature coefficient.

Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM

This paper proposes schemes for the direct measurement of bit-line (BL) voltage swing, sense amplifier (SA) offset voltage, and word-line (WL) pulse width, demonstrated in a 40 nm CMOS 32 kb fully functional SRAM macro with <;2% area penalty. This is the first such scheme to enable the optimal tuning of WL-pulse (WLP) width according to on-site measurement results for BL voltage swing, dynamic read stability, and write margin, all of which depend on WLP width. It also eliminates the need for additional margins related to BL voltage swing, which has conventionally been required to ensure adequate tolerances against simulation errors and inaccurate estimation of SA offset voltage. This opens up possibilities for a more aggressive approach to deal with WLP width instead of only ensuring the target BL voltage swing.

DRAM Yield Analysis and Optimization by a Statistical Design Approach

In this paper the electric yield of DRAM core circuits is investigated by means of a statistical approach that incorporates a hierarchical linear Gaussian model for the DRAM core sensing process and a lognormal distribution model for the DRAM cell leakage. Analytical yield expressions are obtained and found to be dominated by two independent sources-either the lognormal distribution of the cell leakage components or the Gaussian distribution depending on the array structural parameters, parasitic, and the sense amplifier offset voltage. Analytical yield analysis is conducted for several different DRAM architectures and compared to measurements from signal margin analysis and data retention tests. The yield model is found to be very accurate. Thanks to the short computation time, it can be easily applied to the analysis and yield optimization of novel array structures, DRAM cell leakage analysis, sense amplifier offset voltage requirements, and core supply voltage optimization. It also paves the way for the design for yield of other memory circuits.

Zero Error Analysis and Compensation of No-Beat Time Division Multiplier

Time division multiplier was widely used in high-precision industrial frequency AC power measurements.The poor stability of zero point was caused by the switch leakage and amplifier offset voltage. Based on the experimental study of the time division multiplier circuit designed in the article, the mathematical model of zero point compensation was established, and then the appropriate calibration method was proposed. Considered the amplifier offset voltage, the error model of the time division multiplier was analyzed and the error expression was obtained. These can provide theoretical guidance for choosing amplifiers of the no-beat time division multiplier.

Applications of Thermoresistive Sensors Using the Electric Equivalence Principle

In this paper, a survey on the characteristics of thermoresistive sensors [positive temperature coefficient (PTC) and negative temperature coefficient (NTC)] and their applications to measurement structures that use the electric equivalence principle, in special radiometers and anemometers, is presented. The dynamic responses of the architectures and the influence of the operational amplifier offset voltage on the instrument performance are discussed. Alternative architectures employing pulsewidth modulation (PWM) and sigma-delta analog-to-digital (A/D) converters are also shown.

A 12-Bit Ratio-Independent Algorithmic A/D Converter for a Capacitive Sensor Interface

This paper describes a ratio-independent algorithmic analog-digital (A/D) converter architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switches, and some digital logic. The prototype 12-bit, 40-kS/s A/D converter (ADC) with an active die area of 0.041 mm2 is implemented in a 0.13-mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 68.4-muW power dissipation, the ADC achieves 80.2-dB spurious-free dynamic range and 63.3-dB signal-to-noise and distortion ratio.

Right-direct (BI) type wide bandpass SC ladder filter with compensation for finite amplifier gain and offset voltage

In this paper gain- and offset-compensated (GOC) modification of a sixth-order right-direct (BI) type wide bandpass switched-capacitor (SC) ladder filter is proposed. It is based on the use of simple and fast operational amplifiers (op amps) with low but precisely known and stable dc gain A. At first, the conventional integrators in the filter are replaced with GOC integrators and the unswitched capacitors in the capacitive loops are split into two capacitors. Subsequently, the nominal op amps gain value A0 is taking into account in the capacitance sizing of some appropriately chosen capacitors. .

A Sense Amplifier Scheme with Offset Cancellation for Giga-bit DRAM

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with freelevel precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negativelydriven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

Error in the thermoresistive sensor-based feedback measurement configuration due to DC amplifier offset voltage

Feedback circuits with thermoresistive sensors have been widely used in the measurement of thermal radiation and fluid flow. In general, the operation of these circuits is explained, assuming an ideal operational amplifier used in the feedback configuration. The effect of the operational amplifier offset voltage on the static performance has been analyzed. The error introduced when used as a measuring instrument, due to input offset voltage, is estimated.

Variable gain, zero offset, dc coupled video amplifier for microwave detector diodes

A variable gain, zero offset, dc coupled video amplifier has been developed which uses a recently introduced ±5 V operational amplifier with 1.6 GHz gain-bandwidth product. The amplifier is inexpensive and it is particularly suited for amplifying the outputs of microwave diode detectors and driving 50 Ω loads. The large input bias currents of wideband operational amplifiers increase the sensitivity of positive polarity diode detectors, but they decrease the sensitivity when a negative polarity diode detector is used at the amplifier input. To eliminate this effect, matched N-channel junction field-effect transistors (JFETs) are used to buffer the operational amplifier inputs, which reduces the input bias current to ∼1 pA. An added benefit of the JFETs is that the amplifier offset voltage is unaffected by changes in gain or source impedance. Once the offset is zeroed out, it remains zero for all gains and for any combination of diode detectors connected at the input. The maximum attainable gain-bandwidth product is somewhat lower with the JFETs (typically 400 MHz), but the amplifier operates reliably for gains up to 40–50 dB.

A ratio-independent algorithmic analog-to-digital converter combining current mode and dynamic techniques

An algorithmic analog-to-digital converter (ADC) that combines current mode and dynamic techniques is presented. The converter does not rely on high-gain amplifiers or well-matched components to achieve high resolution and is inherently insensitive to the amplifier's offset voltage. An analysis of the converter's limitations indicates that the resolution of practical circuits will be limited by the switch-induced charge injection. Ultimately, however, the kT/C noise leads to an area/resolution tradeoff and the transistor's thermal noise leads to a speed/power tradeoff. A prototype fabricated using a 3- mu m CMOS process achieved 10-bit resolution at a sampling rate of 25 kHz on an area of only 0.18 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Switched-capacitor gain stage with reduced sensitivity to finite amplifier gain and offset voltage

A new switched-capacitor gain stage is presented that exhibits reduced sensitivity to operational amplifier gain and offset voltage. In addition, the design employs fewer switches and capacitors than previous techniques, and is less sensitive to parasitic capacitance effects. It should find wide application in A/D, D/A and other analogue arithmetic building blocks.

A study of the constant-temperature hot-wire anemometer

The conventional ‘bridge-feedback amplifier’ constant-temperature hot-wire anemometer is analysed to determine its static and dynamic response. The effects of moderate feedback amplifier gain, bridge imbalance, stray bridge reactance, amplifier offset voltage, lack of common mode rejection, amplifier frequency response and departure from constant transconducture are included. The root loci of the system are mapped out and the consequences of the analysis are discussed from the viewpoint of both the operator and the designer.