Amplifier Input Research Articles

Dual Push–Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays

This brief presents the experimental validation of a low-power, large output swing, class-AB buffer amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input amplifiers and a dual-path push–pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35- ${\mu }{\text{m}}$ technology and supplied from a 3-V supply, the proposed buffer amplifier can drive a 1-nF column line load within a 1.11- ${\mu }\text{s}$ settling time under a full voltage swing, while drawing only 1.6 ${\mu }\text{A}$ quiescent current and occupying 5562 ${\mu }{\text{m}}^{{2}}$ of silicon area. As compared to the state of the art, the best figure of merit (pF/ ${\mu }\text{s}{\cdot } {\mu }\text{A}$ ) is found.

A Mixed-Signal Circuit Technique for Cancellation of Interferers Modulated by LO Phase-Noise in 4G/5G CA Transceivers

In RF transceivers operating in carrier-aggregation, spurs are generated on the transceiver chip which may down-convert any blocker signal located at the spur frequency into the receiver baseband. The blocker signal could either be the transceiver’s own transmit signal when operating in frequency-division duplex, or a WiFi-related signal received by the antenna. This so-called modulated spur interference contains the phase-noise (PN) of the involved local oscillator harmonics which created the spur and leads to a degradation of the wanted RX signal. The presented mixed-signal circuit mimics the spur building law including the PN of the harmonics and is, therefore, able to provide a replica of the spur interference including PN modulated components. This replica is then used as a reference signal for the digital cancellation of the main and image modulated spur interference using a widely-linear (WL) cancellation structure. The proposed circuit technique is implemented in 28 nm LP CMOS technology, and measurement results show that the mixed-signal solution outperforms a digital-only WL cancellation with respect to PN cancellation even with high blocker power levels of −15 dBm at the input of the low-noise amplifier.

Compact portable indicator-meter of ozone concentration

Compact portable indicator-meter of ozone concentration is the most suitable device to measure the ozone concentration in the work zone and control its maximum allowable concentration. The analysis of existing ozone measurement methods showed that the amperometric method is the most suitable for designing such indicators-meters. Accordingly, two-electrode electrochemical ozone sensors of the amperometric type based on solid and liquid electrolyte are selected as the primary measuring detectors. Studies of possible schemes for constructing input circuits of the indicator-meter showed that it is advisable to connect an ozone sensor with a solid electrolyte directly to the input of an operational amplifier functioning in a current-voltage converter mode without a load resistor. The ozone sensor with a liquid electrolyte is better to connect to a load resistor of 100 Ohms, the signal from which is fed further to the input of an operational amplifier functioning in a voltage converter mode. The structural and schematic diagrams of the ozone concentration indicator are developed and an experimental sample is made. It is calibrated at 4 mg/m3 point using an electrochemical ozone generator. The ozone concentration produced by an electrochemical generator is tested using the iodometric method and the error does not exceed 5 %. The experimental study of the errors of the indicator-meter of ozone concentration with a sensor based on solid electrolyte was conducted in the main measurement range, taking into account its higher sensitivity and lower error of nonlinearity, compared with the sensor based on liquid electrolyte. The experimental study of the errors of the ozone concentration indicator-meter with a sensor based on a liquid electrolyte is conducted in an extended measurement range. For the tests, two series of studies are conducted with an interval of 1,5 months, which made it possible to establish changes in the sensor characteristics. The study results of two variants of an experimental sample of the ozone concentration indicator-meter with solid and liquid electrolyte sensors showed that the relative measurement error does not exceed 25 % in the ozone concentration range of 0,1-10 mg/m3. And in the range of 0,05-0,5 mg/m3 the error value from full scale does not exceed 22 %. These values correspond to the existing standards.

A Novel Configuration of A Microstrip Power Amplifier based on GaAs-FET for ISM Applications

Power Amplifiers (PA) are very indispensable components in the design of numerous types of communication transmitters employed in microwave technology. The methodology is exemplified through the design of a 2.45GHz microwave power Amplifier (PA) for the industrial, scientific and medical (ISM) applications using microstrip technology. The main design target is to get a maximum power gain while simultaneously achieving a maximum output power through presenting the optimum impedance which is characteristically carried out per adding a matching circuit between the source and the input of the power amplifier and between the load and the output of the power amplifier. A "T" matching technique is used at the input and the output sides of transistor for assure in band desired that this circuit without reflections and to obtain a maximum power gain. The proposed power amplifier for microwave ISM applications is designed, simulated and optimized by employing Advanced Design System (ADS) software by Agilent. The PA shows good performances in terms of return loss, output power, power gain and stability; the circuit has an input return loss of -38dB and an output return loss of -33.5dB. The 1-dB compression point is 8.69dBm and power gain of the PA is 19.4dBm. The Rollet's Stability measure B1 and the stability factor K of the amplifier is greater than 0 and 1 respectively, which shows that the circuit is unconditionally stable. The total chip size of the PA is 73.5× 36 mm2.

Design of Wide-band Power Amplifier based on Power Combiner Technique with Low Intermodulation Distortion

RF power amplifiers are one of challenging blocks in designing radio frequency transceivers, this is due to non-linearity behavior of power amplifiers that leads to inter-modulation distortion. This paper presents the design of wide-band power amplifier which combined with parallel coupled line band pass filter at the input and output of power amplifier to allow the only required frequency band to pass through the power amplifier. Class-A topology and ATF-511P8 transistor are used in this design. Advanced Design System software used as a simulation tool to simulate the designed wide-band power amplifier. The simulation results showed an input return loss (S11) which less than -10dB, and gain (S21) is higher than 10 dB over the entire frequency band and considers as flat as well. The designed amplifier is stable over the bandwidth (K>1). Inter-modulation distortion is -56.919dBc which is less than -50dBc with 10dBm input power. The designed amplifier can be used for the microwave applications which include weather radar, satellite communication, wireless networking, mobile, and TV.

APPLICATION OF THE PLL CONTROL AT THE REALIZATION OF A 16-THROUGH ADC

This article describes the method of converting an analog signal into a digital code using a phase locked loop (PLL) circuit. The functional structure of the voltage-to-digital conversion circuit is considered. The application of the principle of phase-locked loop for controlling the duty cycle of the output signal of a phase detector when the voltage at the positive input of the operational amplifier included in the low-pass filter is investigated. In the modern world, analog-to-digital converters (ADCs) are available in almost every electronic device. The application of different ADC architectures is determined by their parameters and features by circuit and technological implementation. The phase-locked loop with a digital part (16-bit counter, storage register and data transfer interface) allows to obtain a precision analog-to-digital converter, based on a relatively simple circuit design, which has high accuracy and low noise level. Negative feedback of the PLL loop makes it possible to level the error of the passive elements of the low-pass filter (LPF) and the voltage controlled oscillator (VCO). The result of this work is an analysis of the ADC characteristics in the technological basis of 250 nm.

Enzyme‐Free Detection of Glucose with a Hybrid Conductive Gel Electrode

AbstractCurrent assays for glucose monitoring rely predominantly on glucose oxidation‐catalyzing enzymes because of the high specificity of enzyme–substrate interactions. Enzymes are however expensive, suffer from instability during fabrication, operation, and storage, and necessitate complex procedures for integration with transducer materials. These challenges, rendering the enzyme‐based sensors disadvantageous for routine glucose monitoring, can be overcome by nonenzymatic sensors. Here, for the enzyme‐free detection of glucose, an electroactive gel is developed via one‐pot polymerization. The functional material is a hybrid of the conducting polymer poly(3,4‐ethylenedioxythiophene):polystyrenesulfonate and a polyacrylamide gel functionalized with phenylboronic acid. As an electrode, the gel exhibits a specific current response to glucose within the standard concentration range measured in the complex blood‐like medium. When integrated as the lateral, micrometer‐scale gate electrode of an organic electrochemical transistor (OECT), the channel current is proven to be sensitive to the presence of glucose in the measurement solution. The advantage of the OECT‐based sensor compared to the amperometric electrode is its miniaturized form, amplified input signal as well the elimination of a reference electrode. Adaptable to different geometries, this conducting gel exhibits multifunctionality within its soft, gel‐like architecture, that is, mixed ionic and electronic conductivity and glucose‐specific electrical response.

Sound quality degradation of audio equipment by hum noise induced by non-audible high frequency electrical noise

In recent audio equipment, induction and inflow of non-audible high frequency (HF) electrical noise to audio equipment is increasing more and more due to implementation of personal computer / network connectivity and high-resolution capability in digital audio equipment. In this study, in order to investigate another causes of influence of non-audible HF electric noise on playback sound, we measured a loudspeaker output of an audio amplifier by the audio analyser with inputting single HF sine wave from a function generator to analog input of the audio amplifier. From measured results, it was found that the power of harmonics of 60 Hz (hum noise) on the loudspeaker output of some audio amplifiers increased when single HF sine wave was inputted. Tendency of the increasing of the hum noise component depended on the frequency of the inputted sine wave and model of audio amplifier. These results show the importance of consideration of HF characteristic and countermeasure to the HF noise also in circuit design and tuning of audio equipment.

A Test Platform for the Noise Characterization of SiGe Microbolometer ROICs

This paper introduces an in-circuit performance evaluation system for SiGe microbolometer readout integrated circuits (ROICs) that can characterize the overall system noise performance by emulating microbolometers with MOSFETs biased in the triode region. Specifically, the proposed test platform is designed for the testing of imagers with high resistance SiGe microbolometers. The architecture of the ROIC is based on a bridge with active and reference bolometer pixels with a capacitive transimpedance amplifier input stage and column parallel integration with serial readout. Noise measurements along with simulated resistance curves of the dummy detectors are reported. The prototype with 17-μm pixel pitch has been designed and fabricated in a 0.25-μm SiGe BiCMOS process.

UWB HABERLEŞME İÇİN BİR DARBE ÜRETEN DEVRENİN TASARIMI

Generation of very short pulses with a pulse width in the order of a few nanoseconds or less is a requirement for an UWB communications system. A pulse generator circuit based on the step-recovery effect of an RF transistor has been designed for the 0-960-MHz UWB system, and is presented in this paper. The pulse generator includes a linear RF amplifier with common-emitter topology and a high-pass filter following the amplifier. Input of the RF amplifier is driven by a clock signal provided by a function generator. Amplifier output includes positive amplitude and negative amplitude pulses due to rising and falling edges of the collector-emitter voltage of the transistor, respectively. Amplifier output is then fed to a high-pass filter. Low-frequency transitions are further filtered out, and the output of the high-pass filter is a pulse train consisting of very short pulses. The pulse width has been measured as about 2.5 ns using a 300-MHz digital oscilloscope.

Enhanced-Selectivity High-Linearity Low-Noise Mixer-First Receiver With Complex Pole Pair Due to Capacitive Positive Feedback

A mixer-first receiver (RX) with enhanced selectivity and high dynamic range is proposed, targeting to remove surface acoustic-wave-filters in mobile phones and cover all frequency bands up to 6 GHz. Capacitive negative feedback across the baseband (BB) amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the BB amplifier, which is upconverted to the RF port to obtain steeper RF bandpass filter roll-off and reduced distortion. This paper explains the circuit principle and analyzes RX performance. A prototype chip fabricated in 45-nm partially depleted silicon on insulator (SOI) technology achieves high out-of-band linearity (input-referred third-order intercept point (IIP3) = 39 dBm and input-referred second-order intercept point (IIP2) = 88 dB) combined with sub-3-dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz.

Self-Oscillating Mode of a Nanoresonator

The paper proposes a new graphene resonator circuit which operates on the principle of a self-oscillator and has no drawbacks typical of nanoresonators as mass detectors and associated with their law quality factor, eigenfrequency errors (measurements from resonance curves), and dependence of quench frequency on oscillation frequency (curves with quenching for nonlinear systems). The proposed circuit represents a self-oscillator comprising an amplifier, a graphene resonator, and a positive feedback loop with a graphene oscillation transducer, and its major advantage is in self-tuning to resonance frequency at slowly varying resonator parameters, compared to oscillation periods. The graphene layer with a conducting substrate beneath it forms a capacitor which is recharged by a dc voltage source as its capacitance varies due to graphene deformation, and the recharge current is an oscillation- dependent signal transmitted from the transducer to the amplifier input. The graphene layer is placed in a magnetic field and is deformed when a current from the amplifier output is passed through. By properly choosing the magnetic field direction and the amplifier gain, it is possible to provide swinging oscillation whose amplitude is limited by the amplifier nonlinearity. For the proposed system we present an electromechanical model, dimensionless equations of motion, and numerical data demonstrating the generation of steady-state oscillations with eigenfrequency. Also presented is an analysis showing that the system can have only one limit cycle and that this cycle is always stable. The proposed resonator circuit can be used as a mass detector which determines the added mass from a change in self-oscillation frequency.

Analysis and Design of a 30- to 220-GHz Balanced Cascaded Single-Stage Distributed Amplifier in 130-nm SiGe BiCMOS

This paper describes a novel distributed amplifier (DA) architecture for ultra-wide band of operation at millimeter-wave frequency. The DA consists of two cascaded single-stage DAs (CSSDAs) embedded in a balanced architecture. The implemented design retains the benefits of CSSDAs in terms of high maximum frequency, broad band of operation, and compact area, while significantly improving the amplifier input and output matching and its linearity with the balanced architecture, which are the major issues of this class of circuits. The small-signal analysis is provided in detail and explains the nature of the poor output matching typical of this class of DAs. Furthermore, the CSSDA gain is calculated as function of frequency and circuit parameters, extending available literature results, and providing direct design guidelines with a compact formula. Experimental validation is demonstrated with the fabrication of a circuit prototype in a 130-nm SiGe BiCMOS process. The circuit is able to provide an average of 16-dB gain over the frequency band 30–220 GHz, with input- and output-return losses above 10 dB, and a maximum measured output-referred 1-dB compression point of 4.5 dBm. To the best knowledge of the authors, the measured matching and linearity are the best reported for CSSDAs.

A Fully On-Chip 80-pJ/b OOK Super-Regenerative Receiver With Sensitivity-Data Rate Tradeoff Capability

This paper presents an ultra-low power super-regenerative receiver suitable for ON–OFF keying modulation and provides analytical insight into its design procedure. The receiver is fabricated in 40-nm CMOS technology and operates in the ISM band of 902–928 MHz. Binary search algorithm through successive approximation register architecture is being exploited to calibrate the internally generated quench signal and the working frequency of the receiver. Employing an on-chip inductor and a single ended to differential architecture for the input amplifier has made the receiver fully integrable, eliminating the need for external components. A power consumption of 320 $\mu \text{W}$ from a 0.65-V supply results in an excellent energy efficiency of 80 pJ/b at 4-Mb/s data rate (DR). The receiver also employs an analog to digital converter that enables soft-decisioning and a convenient sensitivity-DR tradeoff, achieving sensitivity of −86.5, and −101.5 dBm at 1000- and 31.25-kbps DR, respectively.

A current-reuse biomedical amplifier with a NEF < 1

Noise Efficiency Factor (NEF) is the most employed figure of merit to compare different low-noise biomedical signal amplifiers, taking into account current consumption, noise, or bandwidth trade-offs. A small NEF means a more efficient amplifier, and was assumed to be always NEF > 1 (an ideally efficient single BJT amplifier). In this work current-reuse technique will be utilized to exceed this limit in a very efficient CMOS amplifier. A micro-power, ultra-low-noise amplifier, aimed at electro-neuro-graph signal recording in a specific single-channel implantable medical device, is presented. The circuit is powered with a standard medical grade 3.6 V(nom) secondary battery. The amplifier input stage stacks twelve differential pairs to maximize current-reuse. The differential pair stacking technique is very efficient: allows most of the energy to be dissipated in the input transistors that amplify and not in mirror or bias transistors, and allows also the input transistors to operate with a reduced VDS just above saturation. The amplifier was implemented in a 0.6 μm technology, it has a total gain of almost 80 dB, with a 4 kHz bandwidth. The measured input referred noise is 4.5 nV/Hz1/2@1 kHz, and 330 nVrms in the band of interest, with a total current consumption of only 16.5 μA from the battery (including all the 4 stages and the auxiliary circuits). The measured NEF is only 0.84, below the classic NEF = 1 limit.

Leakage current-induced effects in the silicon microstrip and gas electron multiplier readout chain and their compensation method

Leakage current flowing into the charge sensitive amplifier (CSA) is a common issue in many radiation detection systems as it can increase overall system noise, shift a DC baseline or even lead a recording channel to instability. The commonly known leakage current contributor is a detector, however other system components like wires or an input protection circuit may become a serious problem. Compensation of the leakage current resulting from the electrostatic discharge (ESD) protection circuit by properly sizing its components is possible only for a narrow temperature range. Moreover, the leakage current from external sources can be significantly larger. Many applications, especially High Energy Physics (HEP) experiments, require a fast baseline restoration for high input hit rates by applying either a low-value feedback resistor or a high feedback resistance combined with a pulsed reset circuit. Leakage current flowing in the feedback in conjunction with a large feedback resistance supplied with a pulsed reset results in a significant voltage offset between the CSA input and output which can cause problems (e.g. fake hits or instability). This paper shows an issue referred to the leakage current of the ESD protection circuit flowing into the input amplifier. The following analysis and proposed solution is a result of the time and energy readout ASIC project realization for the Compressed Baryonic Matter (CBM) experiment at FAIR (Facility for Antiproton and Ion Research) in Darmstadt, Germany. This chip is purposed to work with microstrip and gaseous detectors, with high average input pulses frequencies (250 kHit/s per channel) and the possibility to process input charge of both polarities. We present measurements of the test structure fabricated in UMC 180 nm technology and propose a solution addressing leakage current related issues. This work combines the leakage current compensation capabilities at the CSA level with high, controllable value of the amplifier feedback resistor independent of the leakage current level and polarity. The simulation results of the double, switchable, Krummenacher circuit-based feedback application in the CSA with a pulsed reset functionality are presented.

Adaptive Nonlinear RF Cancellation for Improved Isolation in Simultaneous Transmit–Receive Systems

This paper proposes an active radio frequency (RF) cancellation solution to suppress the transmitter (TX) passband leakage signal in radio transceivers supporting simultaneous transmission and reception. The proposed technique is based on creating an opposite-phase baseband equivalent replica of the TX leakage signal in the transceiver digital front-end through adaptive nonlinear filtering of the known transmit data, to facilitate highly accurate cancellation under a nonlinear TX power amplifier (PA). The active RF cancellation is then accomplished by employing an auxiliary transmitter chain, to generate the actual RF cancellation signal, and combining it with the received signal at the receiver (RX) low noise amplifier (LNA) input. A closed-loop parameter learning approach, based on the decorrelation principle, is also developed to efficiently estimate the coefficients of the nonlinear cancellation filter in the presence of a nonlinear TX PA with memory, finite passive isolation, and a nonlinear RX LNA. The performance of the proposed cancellation technique is evaluated through comprehensive RF measurements adopting commercial LTE-Advanced transceiver hardware components. The results show that the proposed technique can provide an additional suppression of up to 54 dB for the TX passband leakage signal at the RX LNA input, even at considerably high transmit power levels and with wide transmission bandwidths. Such novel cancellation solution can therefore substantially improve the TX-RX isolation, hence reducing the requirements on passive isolation and RF component linearity, as well as increasing the efficiency and flexibility of the RF spectrum use in the emerging 5G radio networks.

Integrated Quasi-Circulator With RF Leakage Cancellation for Full-Duplex Wireless Transceivers

An integrated reconfigurable CMOS quasi-circulator operating at 2.4 GHz is presented. A passive structure delivers transmit power amplifier (PA) output signal to the differential low-noise amplifier (LNA) input as a common-mode signal and simultaneously delivers received signal as a differential-mode signal at the LNA input. The leakage of the PA output signal at the LNA input is reduced in two steps. First, the use of a reconfigurable impedance matching circuit, instead of a fixed 50- $\Omega $ resistance reduces the leakage by compensating the antenna impedance mismatch, and improves transmitter–receiver isolation. Second, a reconfigurable summing stage adds amplitude and phase adjusted PA output signal to LNA output to cancel the residual PA output leakage. Measurement results show that the receiver achieves a reduction of 90 dB for a single tone and more than 50 dB for a QPSK modulated 40-MHz bandwidth transmit signal. The receiver gain is more than 10 dB and the noise figure in the receiver path is 4.5 dB. The reconfigurable quasi-circulator along with the receiver LNA is designed and fabricated on a 130-nm CMOS technology. The cancellation circuitry occupies 0.27 mm2 and consumes 30-mW quiescent power, while the total active area of the chip is 1 mm2, and it consumes 65-mW power.

Noise in phase-(in)sensitive dual-core fiber parametric amplification.

Flat and wide-bandwidth gain spectrum, along with phase-sensitive gain with no need to generate amplifier input idlers, can be achieved with a coupled dual-core fiber optical parametric amplifier. In this paper, we analyze the noise properties of such an amplifier. We achieve a 3 dB noise figure in the phase-insensitive case and a minimum of -6 dB noise figure in the phase-sensitive configuration. An alternative phase-sensitive configuration is also studied, that avoids the use of idlers at the input of the amplifier, leading to a 3 dB flat spectrum combined noise figure for the output signals. Pump transfer noise in phase-insensitive and phase-sensitive configurations is also studied along with the noise figure variation against the length of the amplifier.

An implantable mixed-signal CMOS die for battery-powered in vivo blowfly neural recordings

A mixed-signal die containing two differential input amplifiers, a multiplexer and a 50 KSPS, 10-bit SAR ADC, has been designed and fabricated in a 0.35 μm CMOS process for in vivo neural recording from freely moving blowflies where power supplied voltage drops quickly due to the space/weight limited insufficient capacity of the battery. The designed neural amplifier has a 66 + dB gain, 0.13 Hz-5.3 KHz bandwidth and 0.39% THD. A 20% power supply voltage drop causes only a 3% change in amplifier gain and 0.9-bit resolution degrading for SAR ADC while the on-chip data modulation reduces the chip size, rendering the designed chip suitable for battery-powered applications. The fabricated die occupies 1.1 mm2 while consuming 238 μW, being suitable for implantable neural recordings from insects as small as a blowfly for electrophysiological studies of their sensorimotor control mechanisms. The functionality of the die has been validated by recording the signals from identified interneurons in the blowfly visual system.