Deposition Of Amorphous Si Research Articles

Silicon eccentric shell nanoparticles fabricated by template-assisted deposition for Mie magnetic resonances enhanced light confinement

We report a structure of silicon eccentric shell particles array, fabricated by the SiO2 particles monolayer array assisted deposition of amorphous Si, for high-efficiency light confinement. The SiO2 particles monolayer array is tailored to regulate its interparticle distance, followed by silicon film deposition to obtain silicon eccentric shell arrays with positive and negative off-center distance e. We studied the Mie resonances of silicon solid sphere, concentric shell, eccentric shell and observed that the eccentric shell with positive off-center e supports superior light confinement because of the enhanced Mie magnetic resonances. Spectroscopic measurements and finite difference time domain simulations were conducted to examine the optical performance of the eccentric shell particles array. Results show that the Mie magnetic resonance wavelength can be easily regulated by the size of the inner void of the silicon shell to realize tunable enhanced light confinement. It was found silicon shell with D = 460/520 nm offered high enhanced light absorption efficiency at wavelength of λ = 830 nm, almost beyond the bandgap of the amorphous silicon.

Investigation of Arsenic Transient Enhanced Diffusion From Emitter Process at 550 °C Si:As RP-CVD Epitaxy Using Disilane Precursor

Reduced Pressure Chemical Vapor Deposition (RP-CVD) Epitaxy bellow 600 °C is studied for 3D sequential integration [1] where cyclic deposition is needed. Another approach can be useful with Si epitaxy at temperature bellow 600 °C : the deposition of amorphous Si on dielectric during non-selective epitaxy combined with solid phase epitaxy regrowth (SPER) to extend the monocrystalline area. Indeed, using temperature above 600 °C during non-selective epitaxy, a polycrystalline Si film is formed on dielectric. This technique has been used in heterojunction bipolar transistor for the non-selective base deposition [2] and can also be used to ensure a fully monocrystalline emitter.Si:As process has been developed at 550 °C using disilane (Si2H6) as Si precursor and Arsine (AsH3) for As precursor. At this temperature, disilane is mandatory to ensure a sufficient growth rate. The disilane process will be compared to a process of reference, using silane (SiH4) precursor at 620 °C. The As dopant concentration targeted is between 1x20 at.cm-3 and 5x20 at.cm-3. Finally, the dopant diffusion is controlled on non-productive Si(100) wafer (NPW), without pattern, by SIMS for both processes before and after thermal budget (720 °C, 1 h + high temperature Spike anneal) to simulate the thermal budget undergone by the emitter.Thanks to the ASTAR system [3] from NanoMEGAS, the crystal orientation and phase maps of the emitter are extracted for both processes (Fig 1.a). ASTAR system is based on the Automated Crystal Orientation Mappings technique used on a Transmission Electron Microscope (ACOM-TEM). With silane precursor, a poly-emitter is generated whereas the emitter is fully monocrystalline with disilane. The amorphous deposition coupled with SPER ensure a fully monocrystalline emitter. SIMS analysis have been performed and show abnormal diffusion of As with disilane process. To understand the causes of the diffusion, both Si:As processes have been reproduced on NPW by full sheet epitaxy. The abnormal diffusion is still observed with the disilane process (Fig 1.b). Compared to diffusion length extracted from [4] (19nm) the diffusion of As is enhanced. Moreover, As enhanced diffusion occurs for low temperature thermal budget (Fig. 1.c).Historically, defects generated from implantation are known to enhance the diffusion length of the dopant. This phenomenon is called Transient Enhanced Diffusion (TED) and it has been studied and observed from dopant implantation [5]. The implantations generate a supersaturation of interstitials defects (such as auto-interstitial) which enhance the dopant diffusion for low temperature thermal budgets. This is a transient effect because the enhanced diffusion occurs in a short time [5]. In our case, several anneal at 720 °C were applied on the disilane Si:As layer from 1 h to 24 h (Fig. 1.d). Most of the diffusion occurs after the annealing at 720 °C, 1 h. These results highlight the transient effect of the As diffusion using disilane process. With the disilane process, TED of As occurs. Indeed, enhanced diffusion of Arsenic appears only for low temperature annealing and the effect is also transient. Compared to implantation which generates defects during the bombardment, low temperature epitaxy generates defects when the growth rate is too high. The molecules from the gas phase are adsorbed on the surface and break down on atoms (called adatom). The adatoms diffuse on the surface to find a suitable site. During low temperature epitaxy, when the growth rate is too high, the adatom don’t have enough time to diffuse on a suitable site and generate defects.Finally, dopant profile analysis will be completed by atomic force microscopy (AFM) and sheet resistance measurement. The AFM will provide an evolution of the surface topography with the annealing. The sheet resistance, coupling with SIMS, will help to extract the deactivation of dopant. The causes of the TED from disilane process at 550 °C will be discussed and experimental results will be provided.[1] L. Brunet et al., IEEE International Electron Devices Meeting (IEDM), 2018[2] Holger Rücker and Bernd Heinemann, Semicond. Sci. Technology, 2018[3] A. Valery, Doctoral dissertation. Université Grenoble Alpes, 2017[4] S. W. Jones, "Diffusion in silicon". IC Knowledge LLC, 2008[5] S. C. Jain, et al., Journal of applied physics, 2002 Figure 1

(Best Student Presentation Award) Reduced Pressure – Chemical Vapor Deposition of Monocrystalline and Polycrystalline Si(:B) and SiGe(:B) Layers on Blanket Wafers

Monocrystalline SiGe alloys can be used instead of monocrystalline Si in order to increase the performances of devices such as heterojunction bipolar transistors (HBTs) [1]. The epitaxial growth of blanket, monocrystalline SiGe layers on Si with a dichlorosilane + germane + hydrochloric acid chemistry was extensively investigated in the literature [2,3]. Similarly, a switch from polycrystalline Si to polycrystalline SiGe can be favorable, for instance, in Complementary-MOS (C-MOS) devices [4,5]. However, the blanket growth by Reduced-Pressure Vapor Deposition (RP-CVD) of polycrystalline Si and SiGe has not been systematically investigated. We have thus performed a one-to-one comparison in terms of growth kinetics and electrically active dopant incorporation between blanket monocrystalline and polycrystalline Si(:B) and SiGe(:B) layers.Epitaxies or depositions were performed, in 300 mm RP-CVD chambers, on two types of templates (Fig.1): i) N-type Si substrates (Fig.1(a)) and ii) poly-Si/oxide/ P-type Si substrates (Fig.1(b)). The poly-Si layer in stack 1.(b) was obtained thanks to amorphous Si deposition followed by annealing at 750 °C, resulting in a poly-Si film. SiH4+HCl+H2 (named Process 1) and SiH2Cl2 (DCS)+HCl+GeH4+H2 (named Process 2) chemistries were used to deposit Si and SiGe layers between 675-750 °C and 10-20 Torr.Monocrystalline and polycrystalline SiGe growth kinetics for two process conditions: i) 750 °C, 10 Torr with a HCl partial pressure of 0.05 Torr and ii) 725 °C, 10 Torr, with a HCl partial pressure of 0.06 Torr, were similar to that in the literature [1-3, 6-8]. As already shown for monocrystalline layers, there was an increase of the intrinsic SiGe growth with the germane partial pressure and the temperature. Meanwhile, it was reduced when adding HCl (Fig.2). Very similar growth rates and evolutions were however obtained whatever the crystalline state of the layers.When diborane was added the gaseous mixture, different behaviors were evidenced depending on i) the crystallinity and ii) the stoichiometry. The Si:B and SiGe:B growth rates increased with the B2H6 flow whatever the chemistry (Fig.3). This was due to a hydrogen desorption increase on boron surface sites [5,10-11]. Growth rates were otherwise higher for monocrystalline than for polycrystalline layers. The electrical resistivities of c-Si:B and c-SiGe:B layers were one decade lower than those of poly-Si:B and poly-SiGe:B layers, however (Fig.4). Resistivity values were otherwise higher for c-Si:B than for c-SiGe:B. This was likely due to i) a better incorporation of B atoms into SiGe than in Si [3,8,9] and ii) a better hole mobility in SiGe [10]. An opposite behavior was observed for polycrystalline layers, with higher resistivities for poly-SiGe:B than for poly-Si:B. We otherwise had similar resistivity evolutions as the partial pressure of diborane Pp(B2H6) increased for all types of layers. A decrease was observed first, followed by a resistivity plateau then some resistivity re-increase for really high diborane flows. Such a phenomenon was already observed for monocrystalline layers and was explained by a crystalline quality degradation [3,8,9] that reduced the hole mobility. A similar behavior was assumed for poly-layers, with a morphological transition to the amorphous phase [11,12]. Top-view Scanning Electron Microscopy (SEM) images (Fig. 5) confirmed the morphological evolution of c-Si:B, poly-Si:B, c-SiGe:B and poly-SiGe:B as the diborane partial pressure increased.New data points for c-SiGe and c-SiGe:B will also be provided for other process conditions. For intrinsic layers, we will show that Refs. [1,2] x2/(1-x) = n×(F(GeH4)/F(SiH2Cl2)) relationship between the Ge concentration x and the germane over dichlorosilane mass-flow ratio is also valid at 10 Torr, with n = 3 at 700 °C with a F(SiH2Cl2)/F(H2) Mass-Flow Ratio (MFR) of 0.005 and a F(HCl)/F(H2) MFR of 0.006. Various characterization techniques were also used to determine the concentration of substitutional Boron atoms in SiGe:B layers and the lattice contraction coefficient (β = 9.11×10-24 cm3). The value of the latter, which is most useful to assess the compressive strain compensation by small boron atoms in SiGe layers, will be compared to literature values.[1] J. Appl. Phys. 88 (2000) 4044[2] J. Crystal Growth 305 (2007) 113[3] J. Crystal Growth 310 (2008) 62[4] J. Microelec. Sys. 16 (2007) 68[5] International Electron Devices Meeting (1991) 567[6] Appl. Phys. Lett. 56 (1990) 1275.[7] S. Chang et al., ECS Proceedings 87–8 (1987) 122[8] J Mater Sci: Mater Electron (2007) 18:747[9] ECS Trans. 75, 8 (2016) 265[10] Mater. Sci. Eng. B 114–115 (2004) 318[11] Appl. Phys. Lett. 66 (1995) 195[12] ECS Trans. 35, 30 (2011) 45 Figure 1

Copper Silicide Nanowires as Hosts for Amorphous Si Deposition as a Route to Produce High Capacity Lithium-Ion Battery Anodes.

Herein, copper silicide (Cu15Si4) nanowires (NWs) grown in high densities from a metallic Cu substrate are utilized as nanostructured hosts for amorphous silicon (aSi) deposition. The conductive Cu15Si4 NW scaffolds offer an increased surface area, versus planar substrates, and enable the preparation of high capacity Li-ion anodes consisting of a nanostructured active material. The formation method involves a two-step process, where Cu15Si4 nanowires are synthesized from a Cu substrate via a solvent vapor growth (SVG) approach followed by the plasma-enhanced chemical vapor deposition (PECVD) of aSi. These binder-free anodes are investigated in half-cell (versus Li-foil) and full-cell (versus LCO) configurations with discharge capacities greater than 2000 mAh/g retained after 200 cycles (half-cell) and reversible capacities of 1870 mAh/g exhibited after 100 cycles (full-cell). A noteworthy rate capability is also attained where capacities of up to 1367 mAh/g and 1520 mAh/g are exhibited at 5C in half-cell and full-cell configurations, respectively, highlighting the active material's promise for fast charging and high power applications. The anode material is characterized prior to cycling and after 1, 25, and 100 charge/discharge cycles, by scanning electron microscopy (SEM) and transmission electron microscopy (TEM), to track the effects of cycling on the material.

Silicon–Germanium bilayer sputtered onto a carbon nanotube sheet as anode material for lithium–ion batteries

In this work, multiwalled carbon nanotube-silicon/germanium (MWCNT-Si/Ge) electrodes were prepared by layer-by-layer deposition of Si and Ge films onto an MWCNT sheet using RF magnetron sputtering. The MWCNT-Si/Ge composites were characterized by spectroscopy and microscopy techniques, which confirmed the deposition of amorphous Si and Ge films. The as-prepared Si/Ge@MWCNT composites were tested as an anode material in a half cell using Li metal as counter and reference electrodes, and in a full cell using LiFePO4 as a cathode. MWCNT-Si/Ge showed a greater charge capacity retention (88% capacity retention) than MWCNT-Si (72% capacity retention) and Cu–Si/Ge (12% capacity retention) after 50 GCD cycles, confirming the important roles of the Ge layer and MWCNT substrate in the enhancement of the performance of Si-based anodes. The results confirmed that the lithium storage performance of the Si film was enhanced by the deposition of the Ge film on the surface. Si/Ge@MWCNT composites exhibited stable electrochemical performance during the first 50 cycles at 500 mA/g, with a reversible specific capacity greater than 1580 mAh/g. The MWCNT-Si/Ge composite anode exhibited a specific charge capacity of 1975 mAh/g at a current density of 200 mA/g, 1725 mAh/g at 500 mA/g, 1635 mAh/g at 1000 mA/g, 1580 mAh/g at 2000 mA/g, and 1472 mAh/g at 3000 mA/g. The MWCNT-Si//LiFePO4 full cell displayed satisfactory cycling performance.

Plasma-enhanced chemical vapor deposition of amorphous Si on graphene

Plasma-enhanced chemical vapor deposition of thin a-Si:H layers on transferred large area graphene is investigated. Radio frequency (RF, 13.56 MHz) and very high frequency (VHF, 140 MHz) plasma processes are compared. Both methods provide conformal coating of graphene with Si layers as thin as 20 nm without any additional seed layer. The RF plasma process results in amorphization of the graphene layer. In contrast, the VHF process keeps the high crystalline quality of the graphene layer almost intact. Correlation analysis of Raman 2D and G band positions indicates that Si deposition induces reduction of the initial doping in graphene and an increase of compressive strain. Upon rapid thermal annealing, the amorphous Si layer undergoes dehydrogenation and transformation into a polycrystalline film, whereby a high crystalline quality of graphene is preserved.

High Performing Hollow Silicon Nanotube Anodes for Lithium Ion Batteries

Silicon has attracted considerable interest as a as a high energy density anode replacement to graphite for lithium ion batteries due to this high theoretical capacity of 4200 mAh/g. The material however suffers from colossal volume expansion (400%) related stresses during cycling leading to pulverization and cracking of the electrode. Over the past few years different approaches have been developed to address the issue caused by the formation of various zintle phases of Li – Si system during the lithiation and alloying process. These approaches involve the use of silicon nanoparticles[1], composite structures of amorphous silicon[2], in-situ and ex-situ active – inactive matrices[3], electrodeposited thin films and VACNT-Si heterostructures[4-6]. Amongst these, silicon nanoparticles and nanotubes have shown the ability to withstand the large internal stresses and strain mismatch generated during the expansion process and hence, serve as stable architectures for exploration and exploitation as an anode in Li/Li+battery. Previously we have demonstrated a simple and large scale synthesis approach for the generation of hollow silicon nanotubes (h-SiNTs) using Inorganic nanowire (I-NW) templates and chemical vapor deposition of amorphous Si which show excellent and stable cycling capacities (2420mAh/g @ 300mA/g) for the Li/Li+system. However, the system shows a high first cycle irreversible (FIR) loss (24%-27%) due to the SEI formation and relatively low columbic efficiency of 98.0% In the present work, we have studied the effect of optimizing the time of deposition of Si during the CVD on the FIR loss and loading density. These hollow Si nanotubes were then coated with a thin layer of carbon by gaseous thermal decomposition at 700oC and further washing with suitable reagents to remove the unwanted phases on the surface. Slurry based electrodes of hollow nanostructures (carbon coated and reagent washed) mixed with binder and conductive additives were then fabricated and tested in a half cell configuration against lithium foil between the voltage range 0.01V – 1V vs. Li/Li+in 1M LiPF6 (dissolved in EC:DEC:FEC=45:45:10) electrolyte. We have demonstrated the increase in loading density of the active material in the electrode by increasing the time of deposition thus, leading to increase in the thickness of the hollow Si nanotube wall. Subsequently, the FIR loss decreases to 15% with the increase in the time of Si – CVD deposition due to the reduction in the specific surface area of the hollow SiNTs however, without affecting the stability of the nanostructured electrodes. The carbon coated hollow SiNTs (Figure 1) showed a first cycle capacity of 1780 mAh/g (at 300mA/g) with FIR loss of only 14.2% and a columbic efficiency of 99.9%. The reagent washed carbon coated hollow SiNTs further exhibited a first cycle capacity of 1800mAh/g (at 300mAh/g) with an FIR loss of only 13% and a columbic efficiency of 99.92%. Materials phase, morphology and surface analysis was conducted on the electrodes before and after electrochemical testing to confirm the stability of the nanostructures on long term cycling. SEM analysis was conducted on the electrode in lithiated state to study the effect of volume expansion on the morphology and configuration of the electrodes. Results of these studies will be presented and discussed. Acknowledgement: The authors gratefully acknowledge financial support of the DOE-BATT (DE-AC02-05CHl1231) and NSF (CBET-0933141) programs. The authors also acknowledge the Edward R. Weidlein Chair Professorship funds and the Center for Complex Engineered Multifunctional Materials (CCEMM) for support of this research.

3-dimensional carbon nanotube for Li-ion battery anode

Carbon nanotubes, in different forms and architectures, have demonstrated good promise as electrode material for Li-ion batteries, owing to large surface area, shorter Li-conduction distance and high electrical conductivity. However, practical application of such Li-ion batteries demands higher volumetric capacity, which is otherwise low for most nanomaterials, used as electrodes. In order to address this urgent issue, we have developed a novel 3-dimensional (3D) anode, based on multiwall carbon nanotubes (MWCNTs), for Li-ion batteries. The unique 3D design of the electrode allowed much higher solid loading of active anode material, MWCNTs in this case and resulted in more amount of Li+ ion intake in comparison to those of conventional 2D Cu current collector. Though one such 3D anode was demonstrated to offer 50% higher capacity, compared to its 2D counterpart, its ability to deliver much higher capacity, by geometrical modification, is presented. Furthermore, deposition of amorphous Si (a-Si) layer on the 3D electrode (a-Si/MWCNTs hybrid structure) offered enhancement in electrochemical response. Correlation between electrochemical performances and structural properties of the 3D anodes highlights the possible charge transfer mechanism.

Effect of exciton migration on the light emission properties in silicon nanocrystal ensembles

Different silicon nanocrystal (Si NC) systems in which Si NCs were either entirely isolated or loosely interconnected were studied by photoluminescence (PL) and time-resolved PL decay measurements in the range between 70 and 290 K, in order to investigate the role of exciton migration in the PL properties. We examined three kinds of samples: (a) two light emitting mesoporous Si (PSi) films with different porosities, grown on p-type Si, (b) a heavily oxidized light emitting anisotropic macroporous Si film, and (c) a film consisted of a Si NC superlattice with six Si NC/SiO2 bilayers, grown by low pressure chemical vapor deposition of amorphous Si (α-Si), followed by high temperature thermal oxidation. In the two mesoporous Si films of the first case, the Si NCs show a degree of interconnection that depends on the porosity, whereas in the two other cases the NCs were isolated by SiO2, the degree of electrical isolation depending on the thickness of the SiO2 interlayer between them. Temperature dependent PL spectra and PL decay times of the different systems correlate well with the ability of excitons to migrate from one NC to another (case of loosely correlated NCs) or remain strongly localized within the Si NCs (case of effectively isolated NCs).

Aromatization and isomerization of 1-hexene over alkali-treated HZSM-5 zeolites: Improved reaction stability

Abstract The HZSM-5 zeolites with micro-mesopore hierarchical porosity have been prepared by the post-synthesis of alkali treatment, and tested in the aromatization and isomerization reactions of 1-hexene in a continuous flow fixed bed. Effects of several variables upon the controlled formation of mesopores have been thoroughly investigated. The results showed that new mesopores could be created and enlarged on ZSM-5 zeolite by increasing the NaOH concentration, temperature and treatment time employed in the alkali treatment, among which the NaOH concentration was the most effective variable in the studied extent. However, excessive high NaOH concentration induced the collapse of zeolite framework, while high temperature and long treatment time induced the backward deposition of amorphous Si onto the zeolite, which would decrease the amount of formed mesopores. When the properly alkali-treated HZSM-5 zeolites were used as catalysts, the reaction activity of 1-hexene was enhanced, and the stabilities of aromatization and isomerization reactions were improved while that of the cracking reaction was deteriorated. These variations of reaction stabilities were associated with the introduction of mesopores over the zeolites, which shortened the diffusion pathlength of the feed/products and reduced the channel blockage.

Effect of laser annealing on crystallinity of the Si layers in Si/SiO 2 multiple quantum wells

We report on continuous-wave laser induced crystallisation processes occurring in Si/SiO 2 multiple quantum wells (MQW), prepared by remote plasma enhanced chemical vapour deposition of amorphous Si and SiO 2 layers on quartz substrates. The size and the volume fraction of the Si nanocrystals in the layers were estimated employing micro-Raman spectroscopy. It was found that several processes occur in the Si/SiO 2 MQW system upon laser treatment, i.e. amorphous to nanocrystalline conversion, Si oxidation and dissolution of the nanocrystals. The speed of these processes depends on laser power density and the wavelength, as well as on the thickness of Si-rich layers. At optimal laser annealing conditions, it was possible to achieve ∼100% crystallinity for 3, 5 and 10 nm thickness of deposited amorphous Si layers. Crystallization induced variation of the light absorption in the layers can explain the complicated process of Si nanocrystals formation during the laser treatment.

Design and fabrication of ultrasmall arrayed waveguide grating multiplexers based on Si nanowire waveguides

The large refractive index difference between Si and SiO2 makes it possible to realize ultrasmall photonic integrated circuits. A 5 × 5 ultracompact arrayed waveguide grating multiplexer based on 500×250 nm Si nanowire waveguides is designed and fabricated by using the technologies of E-beam writing and amorphous-Si deposition. The measured channel spacing is about 1.5 nm (close to the design value) and the channel crosstalk is about −8 dB.

Alternative Catalysts For Si-Technology Compatible Growth Of Si Nanowires

AbstractThe use of Au nanoparticles as catalysts for growth of Si nanowires poses fundamental reliability concerns for applications in Si semiconductor technology. In this work we show that the choice of catalysts can be broadened when the need for catalytic precursor dissociation is eliminated. However, the requirements for selective deposition in a gas phase transport -limited regime become stringent. When competing deposition of amorphous Si can bury the particles faster than the incubation time for VLS growth, no nanowire growth will be initiated. We show that the use of a catalyst such as In, already in a liquid form at the growth temperature, is effective. Therefore, the choice of VLS catalysts among the low melting point metals from the III, IV and V groups is suggested.

Residual stress in Si nanocrystals embedded in a SiO2 matrix

Multiple quantum wells consisting of alternating Si and SiO2 layers were studied by means of Raman scattering. The structures were fabricated by the remote plasma enhanced chemical vapor deposition of amorphous Si and SiO2 layers on quartz substrate. The structures were subjected to a rapid thermal annealing procedure for Si crystallization. The obtained results suggest that the Si layers consist of nanocrystals embedded in an amorphous Si phase. It was found that the silicon nanocrystals inside 2nm thin layers are under high residual compressive stress. Moreover, the metastable Si III phase was detected in these samples supporting the presence of large compressive stresses in the structures. The compressive stress could be relaxed upon local laser annealing.

Location Control of Si Thin-Film Grain Using Ni Imprint and Excimer Laser Annealing

A novel method of locating Si crystal grains by combining Ni imprint and excimer laser annealing (ELA) is demonstrated. Ni imprint is used for the purpose of creating Si crystal nuclei that act as the seed for the subsequent crystallization by ELA. Two Ni-imprint processes were investigated; (1) Ni imprint at the SiO2 substrate surface followed by the deposition of amorphous Si (a-Si), and (2) a-Si deposition on the SiO2 substrate followed by Ni imprint at the a-Si film surface. The annealing used to form nuclei at the imprinted sites was carried out at temperatures below 450 °C. XeCl-laser-based ELA of the sample thus prepared resulted in the formation of about 2 µm sized Si grains at the imprinted sites, whereas the grain consists of several sub-grains radially grown from the center of the grain. The application of Secco's etching to the location-controlled grains formed by Ni imprint at the SiO2 substrate delineated a cavity at the middle of the grain, whereas no cavity was observed in the grains formed by Ni imprint at the a-Si surface. Thus, Ni imprint at the a-Si surface produces higher-quality Si grains than Ni imprint at the SiO2 substrate surface. Details of the experimental conditions used to create the location-controlled grains are described.

Li0.5La0.5TiO3와 Si박막을 갖는 구리 집전체의 Li free 음극으로써의 전기화학적 특성

Li free 음극으로써 구리 foil 집전체에 <TEX>$Li_{0.5}La_{0.5}TiO_3$</TEX> 및 Si 박막을 r.f, 스퍼터링법을 이용하여 증착하고 양극 물질로는 <TEX>$Li[Co_{0.1}Ni_{0.15}Li_{0.2}Mn_{0.55}]O_2$</TEX>를 이용하여 전기화학적 특성을 평가하였다. 박막 증착시 플라즈마 내(in-plasma)와 밖(out of plasma)에 구리 foil을 각각 위치시켰다. X-ray 회절 분석의 경우 각각의 조건에서 <TEX>$Li_{0.5}La_{0.5}TiO_3$</TEX> 및 Si 모두 결정 특성의 차이를 발견할 수 없었다. <TEX>$Li_{0.5}La_{0.5}TiO_3$</TEX>의 경우 플라즈마 내에서 증착된 경우 그리고 Si 경우는 플라즈마 밖에서 증착된 경우 각각 싸이클 특성이 우수한 것으로 나타났다. 이는 <TEX>$Li_{0.5}La_{0.5}TiO_3$</TEX> 경우 결정성이 존재할 경우 이온전도 특성이 우수하며 Si 경우 플라즈마 내에서 성장된 박막이 더욱 치밀하여 충방전 중 부피변화에 더욱 민감하였기 때문으로 판단된다. 이상의 결과로부터 (1)전지 용량을 갖는 5게 의한 표면 개질의 경우 구조적으로 안정할 수 있는 비정질 상의 Si이 보다 더 바람직하며 (2) 이온전도 특성을 보이는 <TEX>$Li_{0.5}La_{0.5}TiO_3$</TEX>와 같은 소재를 이용하여 표면 개질을 할 경우 Li의 확산이 더욱 용이한 구조가 바람직할 것으로 판단된다. Electrochemical properties of Cu foil current collector with a <TEX>$Li_{0.5}La_{0.5}TiO_3$</TEX> Cu a Si thin film deposited by r.f sputtering as an anode for Li free battery were evaluated. The Cu foil current collectors were lied in and out of plasma during sputtering process. The X-ray diffraction results indicated that the as-deposited Si and <TEX>$Li_{0.5}La_{0.5}TiO_3$</TEX> thin films in and out of plasma did not show any crystalline difference. The <TEX>$Li_{0.5}La_{0.5}TiO_3$</TEX> film in plasma and Si film out of plasma showed better cyclability since crystalline <TEX>$Li_{0.5}La_{0.5}TiO_3$</TEX> has much higher ionic conductivity and crystalline Si film is much sensitive far volume change during charge-discharge process. These results suggested that the deposition of amorphous Si on Cu foil current collector is much better for fabrication of Li free battery and it can be useful for the unique battery with a cycling number constraint of below 10.

Stability and electric conductivity of Si-metal surface reconstructions during amorphous Si deposition

Surface reconstruction stability of Si(111) √3 × √3-In, Si(111) √3 × √3-Al, Si(111) 4 × 1-In, Si(111) √3 × √3-Ag, Si(111) 3 × 1-Ag, Si(100) 2 × 1, Si(100) 2 × 3-Na and Si(100) 4 × 3-In surface phases has been studied during Si deposition by observation of electron diffraction fundamental and fractional-order spot attenuation. Previous works regarding their atomic structure have enabled to recognize the relationship between the stability and composition of surface phases. It was found that ordered surface phases consisting of adsorbate atoms atop the bulk-like terminated Si surface are unstable and become disordered at the early stages of amorphous (α) Si deposition. The deposition of α-Si on surface reconstructions at 100K results in a delay of disorder process. It was shown that crystal structure of surface phases formed by both adsorbate and substrate atoms has high stability at room temperature (RT) as well as at low temperature (LT). The surface conductivity of buried surface phases was investigated in situ. It was found that the surface conductivity correlates with surface structures’ stability, i.e. the conductivity of ordered surface phases consisting of only adsorbate atoms decreases rapidly, while surface reconstructions that are stable to α-Si deposition are characterized by permanent conductivity.

Origins of growth stresses in amorphous semiconductor thin films.

Stress evolution during deposition of amorphous Si and Ge thin films is remarkably similar to that observed for polycrystalline films. Amorphous semiconductors were used as model materials to study the origins of deposition stresses in continuous films, where suppression of both strain relaxation and epitaxial strain inheritance provides considerable simplification. Our data show that bulk compression is established by surface stress, while a subsequent return to tensile stress arises from elastic coalescence processes occurring on the kinetically roughened surface.

Challenges in Integrating the High-K Gate Dielectric Film to the Conventional Cmos Process Flow

ABSTRACTZrO2 and HfO2 and their alloys with SiO2 are currently among the leading high-k materials for replacing SiOxNy as the gate dielectric for the sub-100 nm technology nodes. International SEMATECH (ISMT) is currently investigating integration issues associated with this required change in materials. Our work has focused on the integration of ALCVD deposited ZrO2 and HfO2 with an industry standard conventional MOSFET process flow with poly-Si electrode. Since the impact of contamination by these new high-k materials introduced in a production fab has not yet been established, it becomes very critical to prevent cross- contamination through the process tools in the fab. A baseline study was completed within ISMT's fab and appropriate protocols for handling high-k materials have been established. The integrated high-k gate stack in a conventional transistor flow should not only meet all the performance requirements of scaled transistors, but the gate dielectric film should be able withstand high-temperature anneal steps. Reactions between ZrO2 and Si have been observed at temperatures as low as 560°C (during the amorphous Si deposition process). Various wet chemistries were also evaluated for removing the high-k film inadvertently deposited on wafer backside, and it was found that ZrO2 etches at extremely slow rates in the majority of the common wet etch chemistries available in a fab. A new hot HF based process was found to be successful in lowering Zr contamination on the wafer backside to as low as 1.8 E10 atoms/cm2. The patterning of a high-k gate stack with poly-Si electrode is another area that required considerable focus. Various dry (plasma) etch and wet etch chemistries were evaluated for etching ZrO2 using both blanket films as well as wafers with patterned poly-Si gate over the high-k films. On the full CMOS flow device wafers, most of these wet chemistries resulted in severe pitting in the ZrO2 film remaining over the source/drain (S/D) areas, as well as in the Si substrate and the field oxide. A poly-Si gate over ZrO2 gate dielectric film was successfully patterned using the standard poly-Si gate etch (Cl2/HBr) for the main etch, followed by a combination of HF and H2SO4 clean for removing all of the ZrO2 remaining over the S/D area. This allowed the fabrication of low-resistance contacts to transistor S/D areas, which ultimately resulted in demonstration of functional transistors with high-k gate dielectric films.

Fabrication of high performance GaN modulation doped field effect transistors

Fabrication of GaN devices presents a number of processing issues. Since the AlGaN/GaN material and sapphire substrates are transparent in the ultraviolet, light scattering can degrade the quality of the lithography. GaN and AlGaN are chemically inert materials, highly resistant to wet etching. Schottky contacts are fabricated with noble metals (Pt, Au) which present adhesion problems. The approaches to solving these difficulties and the routes to fabrication of high performance GaN-based modulation doped field effect transistors are presented. The light scattering has been addressed by the deposition of amorphous Si on the backside of the wafers. Mesa etching for device isolation has been performed with both chemically assisted ion beam etching and a newly developed wet etching technique. Finally, metal adhesion has been greatly improved by the initial deposition of a thin sputtered Pt layer, followed by a thick layer of Pt/Au by e-beam evaporation. A 100 μm wide device showed a maximum dc current density of 946 mA/mm, a peak transconductance of 160 mS/mm, a short circuit current gain cutoff frequency of 15.6 GHz, and a maximum oscillation frequency of 49.4 GHz.