Amorphous InGaZnO Thin-film Transistors Research Articles

Atmosphere Effect in Post-Annealing Treatments for Amorphous InGaZnO Thin-Film Transistors with SiOx Passivation Layers.

We investigated the electrical performance and positive bias stress (PBS) stability of the amorphous InGaZnO thin-film transistors (a-IGZO TFTs) with SiOx passivation layers after the post-annealing treatments in different atmospheres (air, N2, O2 and vacuum). Both the chamber atmospheres and the device passivation layers proved important for the post-annealing effects on a-IGZO TFTs. For the heat treatments in O2 or air, the larger threshold voltage (VTH) and off current (IOFF), smaller field-effect mobility (μFE), and slightly better PBS stability of a-IGZO TFTs were obtained. The X-ray photoemission spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS) measurement results indicated that the oxygen atoms from the ambience led to less oxygen vacancies (VO) and more oxygen-related defects in a-IGZO after the heat treatments in O2 or air. For the annealing processes in vacuum or N2, the electrical performance of the a-IGZO TFTs showed nearly no change, but their PBS stability evidently improved. After 4500 seconds’ stressing at 40 V, the VTH shift decreased to nearly 1 V. In this situation, the SiOx passivation layers were assumed to effectively prevent the oxygen diffusion, keep the VO concentration unchanged and refuse the oxygen-related defects into the a-IGZO films.

Self-Heating Stress-Induced Severe Humps in Transfer Characteristics of Amorphous InGaZnO Thin-Film Transistors

Under a self-heating stress (SHS), amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) would exhibit a severe hump in the transfer characteristics. A model based on state transformation of oxygen vacancies is proposed to explain this phenomenon. The channel region of TFT is considerably self-heated if a large current flows through due to the poor thermal conductivity of a-IGZO. The temperature in the channel region can be raised with the high-power SHS so high that the oxygen vacancies there perform a state transformation from deep-donors and/or traps to shallow-donors, making the carrier concentration increase remarkably in the a-IGZO channel layer. The temperature is highest in the center of channel region and thus the state transformation takes place there first, leading to the carrier concentration increasing there first. As a result, the TFT has a lower turn-on voltage in the central channel region than in the rest, bringing finally about the hump in the transfer curves. The model is well verified by annealing the a-IGZO, which shows that the carrier concentration surely increases greatly when the annealing temperature is over 300 °C.

High-Performance Amorphous InGaZnO Thin-Film Transistor Gated by HfAlOₓ Dielectric With Ultralow Subthreshold Swing

We report a high-performance transparent amorphous indium gallium zinc oxide thin-film transistor (a-IGZO TFT) gated by atomic layer deposition (ALD)-deposited HfAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> . Through a postfabrication annealing optimization process, the total trap density of the device can be reduced in two orders of magnitudes. The subthreshold swing (SS) reaches an ultralow level of 62.29 mV/dec due to the low defect states. A large <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\text{ON}}/I_{\text{OFF}}$ </tex-math></inline-formula> and a high mobility of 2.76 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10^{{9}}$ </tex-math></inline-formula> and 18.94 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> can be achieved, respectively. In addition, the devices exhibit good stability in terms of positive bias stress, thermal, and aging tests. The defect optimization process has been verified by the X-ray photoelectron spectroscopy analysis. Finally, a resistor-loaded inverter was constructed, which showed ideal swing characteristics and its voltage gain was as high as 39 at 7 V. These results indicate such a-IGZO TFT is of great potential for the emerging electronics, large-area display, and other low-power electronics.

Temperature dependence and functionalization of solution processed high-k hybrid gate insulators for high performance oxide thin-film transistors

We demonstrate a solution processed gate insulator (GI) with high dielectric constant (high-k) of up to ∼8.9 for high performance and low voltage operation amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). High mobilities of up to ∼30 cm2 V s−1, threshold voltage of <0.5 V, and low off current (∼10−12 A) can be achieved through the combination of high-k BaTiO x (BTO) nanoparticles and a polysiloxane (PSX) polymer matrix. This combination enables a lower process temperature of 300 °C from 650 °C while ensuring enhanced performance and low gate leakage current. We also show the tunability of the high-k hybrid BTO/PSX through fluorination and addition of a photosensitive property to further reduce the leakage current and inhibit dry etching related degradation. High-k hybrid BTO/PSX GI is a promising candidate for high performance and low-voltage operation oxide TFTs.

Thermal Annealing Improved Stability of Amorphous InGaZnO Thin-Film Transistors Under AC Bias Stresses

Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) severely degrade under AC gate bias stress and AC drain bias stress, whose transfer curves respectively undergo positive shifts of 6.3 and 14.2 V after a stress time of 3000 s with a stress amplitude of 20 V. In this study, annealing at 400 °C in O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> atmosphere is performed to effectively reduce the acceptor-like trap states in the a-IGZO channel and the electric field in the etching-stop layer under the extended drain electrode, which participate in dynamic and DC degradation mechanisms, respectively. Thus, a-IGZO TFTs exhibiting excellent stability without any shift of the transfer curve under the same AC gate bias stress and AC drain bias stress are experimentally demonstrated simultaneously.

Influence of metallization process on solution-processed InGaZnO thin film transistors

Low-temperature solution-processed InGaZnO (IGZO) thin film transistors (TFTs) have recently attracted significant attention as the next-generation flexible display TFTs, owing to their high transparency, high electrical performance, low-cost fabrication, and large-area scalability. However, solution-processed amorphous IGZO TFTs have several drawbacks, such as poor film quality or low stability, and have been studied with view to improving the device performance. One of the critical components determining device characteristics is the metallization process, which we systematically studied using aluminum (Al) source and drain electrodes. The electrical properties were measured for different channel lengths and evaluated using the threshold voltage (V th) and subthreshold swing (SS). Al electrodes directly affect the channel region, enhancing the electron density because of the doping effect from Al and oxygen vacancy-related oxidation of Al and causing an abnormal negative shift of V th, which is confirmed by the component analysis via various spectroscopies. To understand and improve the TFT characteristics, we conducted a low-temperature post-annealing process and polymer passivation and succeeded in moving V th from over 150 V to near 0 V and remarkably improved SS. This study discovered that the influence of source-drain metallization on the channel region determines the device characteristics through the close relation between metal oxidation and the number of oxygen vacancies.

Role of in-situ hydrogen plasma treatment on gate bias stability and performance of a-IGZO thin-film transistors

This work investigates the effect of an in situ hydrogen plasma treatment on gate bias stability and performance of amorphous InGaZnO thin-film transistors (TFTs) deposited by using atmospheric-pressure PECVD. The H2 plasma-treated a-IGZO channel has shown significant improvement in bias stress induced instability with a minuscule threshold voltage shift (ΔV th) of 0.31 and −0.17 V under positive gate bias stress (PBS) and negative gate bias stress (NBS), respectively. With the aid of the energy band diagram, the proposed work demonstrates the formation of negative species O2 − and positive species H2O+ in the backchannel under PBS and NBS in addition to ionized oxygen vacancy (Vo) defects at a-IGZO/ZrO2 interfaces are the reason for gate bias instability which could be effectively suppressed with in situ H2 plasma treatment. From the experimental result, it is observed that the electrical performance such as field-effect mobility (μ FE), on-off current ratio (I on/I off), and subthreshold swing improved significantly by in situ H2 plasma treatment with passivation of interface trap density and bulk trap defects.

Quantitative analysis of defect states in amorphous InGaZnO thin-film transistors using photoinduced current transient spectroscopy

The device and defect characteristics of amorphous indium–gallium–zinc oxide (In:Ga:Zn = 1:1:1 at.%) thin-film transistors (TFTs) as a function of the oxygen partial pressure were investigated. It was found that as the oxygen partial pressure increased, the field effect mobility decreased, the threshold voltage saw a positive shift, and this shift of threshold voltage increased under a negative gate bias stress. From our qualitative analysis of defect states below the conduction band, it was found that as the oxygen partial pressure increased, defect states in the shallow levels decreased, while defect states in the deep levels increased. A quantitative analysis of the defect states in the TFT structures was conducted using photoinduced current transient spectroscopy. It was found that as the oxygen partial pressure used during fabrication of the TFTs increased from 0% to 10% to 60%, the defect states in the shallow levels decreased from 2.74 × 1018 to 2.93 × 1017 to 3.55 × 1016 cm−3, while the defect states in the deep levels increased from non-availability to 1.86 × 1016 to 3.25 × 1016 cm−3. As the oxygen partial pressure increased, the decrease in shallow level defect density is strongly related to a decrease in carrier concentration; the increase in deep level defect density affects the mobility and causes device instability.

Enhanced screening on remote phonon scattering in InGaZnO thin-film transistor by using Ge gate electrode

Room-temperature-processed amorphous InGaZnO thin-film transistors (TFTs) with three different semiconductors (Si, GaAs, and Ge) of various doping concentrations as gate electrodes are fabricated. Like the conventional Si gate devices, both their GaAs and Ge counterparts show carrier mobility increasing with increasing gate doping concentration, further supporting that the holes at/near the surface of a p-type gate electrode can have a screening effect on the remote phonon scattering caused by the surface phonons of their high-k gate dielectrics. Moreover, for the same gate doping concentration, the Ge gate device has a carrier mobility about three times that of its conventional Si gate counterpart. This implies that lower-mass charge carriers in the gate electrode could have a stronger screening effect on remote phonon scattering. As a result, even with a moderate gate doping concentration of 1.0 × 1018 cm−3, the room-temperature-processed Ge gate device shows a high carrier mobility of 60.8 cm2/V s. The enhanced screening effect of the Ge gate electrode should be due to its higher-energy plasmons, which could couple more strongly with the phonons of the gate dielectric to result in weaker gate-dielectric vibration.

Hydrogen Incorporation Modulates Subgap Density of States in Amorphous InGaZnO Thin-Film Transistors

Incorporation of hydrogen into the channel layer of an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor leads to a negative shift in the transfer curve threshold voltage; the magnitude of the threshold voltage shift increases with increasing hydrogen content. Although several atomic models for hydrogen incorporation into a-IGZO have been proposed, hydrogen-induced changes in the sub-gap density of states have never before been directly measured. By employing ultrabroadband photoconduction (UBPC),1,2 we directly observe a large increase in the near-valence band UBPC response in hydrogen-enriched devices; the increase in UBPC response scales with hydrogen concentration.3 This UBPC trend is consistent with the formation of OH states resulting from the interaction of incorporated hydrogen with oxygen already present in the a-IGZO channel layer and explains the observed negative threshold voltage shift in the device transfer curve. K. T. Vogt, C. Malmberg, J. Buchanan, G. Mattson, M. Brandt, D. Fast, P. H.-Y. Cheong, J. F. Wager, M. W. Graham, (2020) Ultrabroadband Density of States of Amorphous In-Ga-Zn-O, Phys Rev Res, 2, 033358K. T. Vogt, G. W. Mattson, J. F. Wager, M. W. Graham (2020) Ultrabroadband Photoconduction Response of Sub-gap Defects in Amorphous In-Ga-Zn-O Thin Film Transistors, ECS Transactions, 97 (7), 339-357G. W. Mattson, K.T. Vogt, C. Malmberg, P. H.-Y. Cheong, J. F. Wager, M. W. Graham, (2020) Effect of hydrogen incorporation on sub-gap density of states in amorphous InGaZnO thin-film transistors, Proc. SPIE, Oxide-based Materials and Devices XI, 112811G, doi.org/10.1117/12.2545439 Figure 1

Degradation and its fast recovery in a-IGZO thin-film transistors under negative gate bias stress* *Project supported in part by the National Natural Science Foundation of China (Grant Nos. 61971299 and 61974101), the Natural Science Foundation of JiangsuProvince, China (Grant No. SBK2020021406), the Fund from the State Key Laboratory of ASIC and System, Fudan University (Grant No. 2019KF007), theFund from the

A new type of degradation phenomena featured with increased subthreshold swing and threshold voltage after negative gate bias stress (NBS) is observed for amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs), which can recover in a short time. After comparing with the degradation phenomena under negative bias illumination stress (NBIS), positive bias stress (PBS), and positive bias illumination stress (PBIS), degradation mechanisms under NBS is proposed to be the generation of singly charged oxygen vacancies () in addition to the commonly reported doubly charged oxygen vacancies (). Furthermore, the NBS degradation phenomena can only be observed when the transfer curves after NBS are measured from the negative gate bias to the positive gate bias direction due to the fast recovery of under positive gate bias. The proposed degradation mechanisms are verified by TCAD simulation.

Introducing effective temperature into Arrhenius equation with Meyer-Neldel rule for describing both Arrhenius and non-Arrhenius dependent drain current of amorphous InGaZnO TFTs

The drain current of the amorphous InGaZnO thin-film transistors (TFTs) shows the Arrhenius and the non-Arrhenius dependence at the high temperature and the low temperature respectively. The gate-voltage-dependent effective temperature is introduced into the Arrhenius equation. Considering the normal Meyer-Neldel (MN) rule and the inverse MN rule, the equation successfully describes both the Arrhenius and the non-Arrhenius dependent drain current at the low and the high gate voltage. The calculated results of the equation are verified by the available experimental data of the amorphous La-doped InZnO TFT and the amorphous InGaZnO (InO3:Ga2O3:ZnO = 1:1:1 mol%) TFT.

Hot-Carrier Effects in a-InGaZnO Thin-Film Transistors Under Pulse Drain Bias Stress

The degradation mechanism of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under pulse drain bias stress is investigated. Although the degradation mechanism is found to be a dc one, the shift of the transfer curve under the pulse drain bias (0-20 V) is unexpectedly larger than that under dc drain bias (20 V) within the same equivalent stress time. The degradation mechanism is proposed to be tunneling and trapping of electrons in the etching stop layer during the pulse peak time and that in the gate dielectric during the pulse base time under the extended drain electrode region of the a-IGZO TFT, where the occurrence of the latter is triggered by the former. A solution for enhancing the stability of the a-IGZO TFT is also suggested.

Effect of ALD- and PEALD- Grown Al2O3 Gate Insulators on Electrical and Stability Properties for a-IGZO Thin-Film Transistor

This study investigated the electrical and stability characteristics of Al2O3 as a gate insulator, which was deposited by various atomic layer deposition methods in top-gate staggered amorphous InGaZnO (a-IGZO) thin film transistors. A trimethylaluminum precursor was used as an Al source, and H2O gas (H2O device) and O2 plasma with a long plasma time (O2 LP device) and a short plasma time (O2 SP device) were used as oxidants. The initial electrical characteristics, including the hysteresis, on–off current ratio, and subthreshold swing, were superior in the H2O device compared to the O2 LP and O2 SP devices. In the positive bias stress (PBS) results, the degradation characteristics showed a tendency similar to the transfer properties. However, under the negative bias illumination stress (NBIS), the stability of the H2O device was significantly reduced compared to the O2 LP and O2 SP devices. In this paper, the mechanism of instability, which has opposite results in terms of the PBS and NBIS for the three devices, was identified using capacitance–voltage, three-terminal charge pumping as electrical analysis techniques and secondary ion mass spectroscopy (SIMS) as a physical analysis technique. It was confirmed that the surface oxidation of a-IGZO deteriorates the interfacial properties, causing the transfer characteristics to degrade. The carbon of the Al2O3 film identified via SIMS analysis acts as a trap layer, causing deterioration in the PBS. Alternatively, in the NBIS, it was observed that the carbon acts as a capture site for photo-excited holes, thereby promoting device stability.

Observation of Hydrogen-Related Defect in Subgap Density of States and Its Effects Under Positive Bias Stress in Amorphous InGaZnO TFT

In amorphous oxide semiconductors, hydrogen-related defects have been unable to be observed from the electrical characteristics of thin-film transistors (TFTs) in comparison to oxygen-related defects. Here, the hydrogen-related defect is observed as the Gaussian distributed density of states (DoS) in ${E}_{\text {C}}-{0.6}$ eV level by using the photoresponse of C-V characteristics in In-Ga-Zn-O (IGZO) TFTs. Coupled with X-ray photoelectron spectroscopy (XPS), it is identified as hydroxide ion (OH−), which both passivates oxygen vacancy defects and supplies the carriers as shallow donors. Furthermore, the evolution of DoS under positive bias stress and its origin are comparatively investigated for IGZO TFTs with three types of gate insulators (GIs), such as low-temperature atomic layered deposited Al2O3, thermally grown SiO2, and double-layered GIs.

Metal Reaction-Induced Bulk-Doping Effect in Forming Conductive Source-Drain Regions of Self-Aligned Top-Gate Amorphous InGaZnO Thin-Film Transistors.

In this paper, the aluminum (Al) treatment-induced doping effect on the formation of conductive source-drain (SD) regions of self-aligned top-gate (SATG) amorphous indium gallium zinc oxide (a-InGaZnO or a-IGZO) thin-film transistors (TFTs) is systematically investigated. Average carrier concentration over 1 × 1020 cm-3 and sheet resistance of around 500 Ω/sq result from the Al reaction doping. It is shown that the doping effect is of bulk despite the treatment at the surface. The doping process is disclosed to be a chemical oxidation-reduction reaction, that generates defects of oxygen vacancies and metal interstitials at the metal/a-IGZO interface. Both the generated oxygen vacancies and metal interstitials act as shallow donors, and the oxygen vacancies diffuse rapidly, leading to the bulk-doping effect. The fabricated SATG a-IGZO TFTs with the Al reaction-doped SD regions exhibit both high performance and excellent stability, featuring a low width-normalized SD resistance of about 10 Ω cm, a decent saturation mobility of 13 cm2/(V s), an off current below 1 × 10-13 A, a threshold voltage of 0.5 V, a slight hysteresis of -0.02 V, and a less than 0.1 V threshold voltage shift under 30 V gate bias stresses for 2000 s.

Roles of Gate Voltage and Stress Power in Self-Heating Degradation of a-InGaZnO Thin-Film Transistors

Roles of gate voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and stress power in self-heating (SH) degradation of amorphous InGaZnO thin-film transistors have been clarified. Normally observed positive threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) shift is attributed to the electron trapping mechanism, which is enhanced by both the effective V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and stress power. The effective V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> plays a dominant role in most cases, while stress power takes control only if it is high enough. Following the positive V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift, a second-stage negative V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> backshift is also observed and is attributed to the water-related positive charges generation mechanism. It is enhanced by both stress power and effective V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> for which stress power is found to be the dominant factor.

Degradation Behavior of Etch-Stopper-Layer Structured a-InGaZnO Thin-Film Transistors Under Hot-Carrier Stress and Illumination

Etch-stopper-layer (ESL) structured amorphous InGaZnO thin-film transistors (a-IGZO TFTs) were fabricated in this article. Degradation behavior of the a-IGZO TFTs under hot-carrier stress and illumination (HCIS) was investigated. As HCIS time increases, the transfer curve in the saturation region shifts in the negative direction under the forward-operation mode, whereas it shifts in the positive direction under the reverse-operation mode. The HCIS-induced degradation behavior was attributed to charge trapping in the IGZO/ESL interface. To examine the degradation mechanism, the capacitance–voltage measurements were performed. After applying HCIS, it is found that the gate-to-drain capacitance curve shifts in the positive direction and the gate-to-source capacitance curve exhibits two-stage rises. Technology computer-aided design (TCAD) was used to simulate the electric field distribution during the stress, which also confirmed the proposed mechanism.

Improved Performance of InGaZnO Thin-Film Transistor With Ti Incorporation Into La2O3 Gate Dielectric

The effects of Ti incorporation in La2O3 gate dielectric on the electrical characteristics of amorphous InGaZnO thin-film transistor are studied. Compared to the control sample with La2O3 gate dielectric, the device performance can be significantly improved with an appropriate Ti dose. Accordingly, the sample with a Ti/(Ti+La) ratio of 6.7% presents a high saturation mobility of 28.1 cm2V−1s−1, small subthreshold slope of 0.17 V/dec, large on/off current ratio of $7.2\times 10$ 7, and acceptable hysteresis. We attribute such an improvement to the passivation of the defect states at/near the La2O3/InGaZnO interface as well as the enhancement of moisture resistance of La2O3 film due to Ti incorporation. However, excessive Ti incorporation leads to device degradation, which is due to more oxygen vacancies generated in gate dielectric.

Abnormal Negative Bias Stress Instability of Amorphous InGaZnO Thin Film Transistors

The negative bias stress normally yields a negative threshold voltage shift of the thin film transistors due to the additional positive charges trapped in the gate dielectrics or at channel/gate insulator interface. However, a positive threshold voltage shift of the device with the post InGaZnO deposition annealing at 400oC is observed in our devices. The Na+ incorporation from Mo gate into the gate dielectric after 400oC annealing is responsible for this abnormal threshold voltage shift. The movement of Na+ ions toward the gate electrode by the negative gate bias decreases the distance between the gate electrode and the Na+ ions. Therefore, the voltage drop between the gate electrode and the Na+ ions reduces, and a corresponding positive threshold voltage shift is observed. Inserting a SiNx layer between the SiOx gate insulator and the Mo gate electrode can reduce the Na+ mobility, and thus a normal negative threshold voltage shift resumes. Experiment: A Mo layer with the thickness of 100 nm was sputtered on glass, and patterned as the gate electrode. Then 300 nm thick SiOx was deposited on the Mo gate electrode by plasma enhanced chemical vapor deposition (PECVD) at 350oC. A 50 nm a-IGZO active layer was sputtered on SiOx. PDA was performed with an O2/N2 gas with a mixing ratio of 1:4, and the annealing temperature is 350oC or 400oC for 1 hour. A 200 nm SiOx layer was deposited on the active layer by PECVD at 200oC as the etch-stop layer. After that, 100 nm Mo was sputtered as the source and drain electrodes. The channel width and length of all TFTs are 20μm and 10μm, respectively. Additional 100 nm thick SiOx was deposited by PECVD at 200oC as the passivation layer. Result and Discussion: The slightly negative VT shift of the device with 350oC PDA after negative bias stress (NBS) was mainly attributed to the hole-trapping in the gate insulator [1] or at the a-IGZO/gate insulator interface [2]-[3]. As the trapped holes increase, the VT shifts to the negative direction. However, the abnormally negative VT shift of the device with 400oC PDA after NBS was due to the motion of mobile Na+ in the gate insulator [4]. The Mo electrode has the Na+ concentration of ∼1×1015 cm−3, which was confirmed by second ion mass spectroscopy (SIMS). These results suggest that the origin of Na+ may be due to the contamination or the purity of Mo target. On the other hand, the peak concentration of Na+ in the device with 400oC PDA is approximately 5X of 350oC PDA. Fig. 1 shows the transfer characteristics of devices after NBS prebiased with a positive gate voltage (VGS=20V for 600 seconds). The larger positive VT shift of 400oC PDA TFT with prebias after NBS than the fresh devices is due to the large movement of Na+ toward gate electrode. Fig. 2(a) and (b) shows the band diagram to illustrate the Na+ effect. During the prebias period, Na+ near the SiOx/Mo gate electrode interface drifts toward the a-IGZO channel. When negative bias is applied at the Mo gate, Na+ moves toward the gate electrode. As the distance between Na+ and gate electrode decreases, the negative voltage drop at the gate electrode decreases, which “effectively” shifts the VT to the positive direction. In order to reduce the impact of Na+ movement, a 50nm SiNx layer was inserted between the SiOx insulator and the Mo gate electrode, and the VT shift after NBS with prebias recovered to negative direction. For SIMS measurement, the peak concentration of Na+ near SiOx and SiNx interface of the device with SiNx layer are smaller than near SiOx and Mo interface of the device without SiNx layer. On the other hand, the Na+ trapped in SiNx has low mobility and relatively low movement during NBS [5]. Therefore, the effectively positive voltage shift caused by Na+ movement is suppressed, and thus improves the reliability of 400oC PDA device. Acknowledgement: The support of INNOLUX and the Ministry of Science and Technology, Taiwan (MOST 108-2622-8-002-016, MOST 108-2218-E-002-027) is highly acknowledged.[1] Y. K. Moon et al., JJAP (2009) [2] E. N. Cho et al., Trans. Device Mater. Rel. (2011) [3] W. T. Chen et al., EDL (2011)[4] C. Lo et al., J-EDS (2016) [5] B.-D. Choi et al., JJAP (2005) Figure 1