Amorphous Indium Gallium Zinc Oxide Thin-film Transistors Research Articles

Asymmetrical degradation behaviors in amorphous InGaZnO thin-film transistors under various gate and drain bias stresses

The asymmetrical degradation behaviors of amorphous indium–gallium–zinc oxide thin-film transistors are studied comprehensively under various gate and drain bias stresses. The transfer curve moves to the negative direction after bias stresses are applied, and different types of asymmetrical degradation are observed depending upon the magnitude of the applied gate and drain bias stresses. After the application of gate-to-source (VGS) and drain-to-source (VDS) bias stresses of (VGS = 16 V, VDS = 16 V) and (VGS = 22 V, VDS = 10 V), the forward mode transfer curve exhibits a more negative shift compared to that of the reverse mode, whereas opposite results are observed under the stress condition of (VGS = 10 V, VDS = 25 V). From the two-dimensional simulation results and the separately extracted subgap density of states in the source and drain sides of the thin film transistors before and after the application of various bias stresses, the local high electric field-induced nonuniform generation rate of the subgap states near the conduction band edge is considered to be the dominant mechanism causing the asymmetrical degradation of the devices under various gate and drain bias stresses. The generation of the subgap states is observed at different locations depending upon the magnitude of the applied gate and drain bias stresses.

Effect of Bulk-Accumulation on Switching Speed of Dual-Gate a-IGZO TFT-Based Circuits

The effect of bulk accumulation on switching speed of dual-gate amorphous indium–gallium–zinc-oxide thin-film transistor (TFT)-based circuits is investigated. Given that bulk accumulation is achieved by synchronized driving of the top gate (TG) and bottom gate, it can be modulated by varying the length of the TG ( $\textrm {L}_{{{\textrm {TG}}}}$ ) for fixed source–drain distance ( $L$ ). It is confirmed from fabricated ring oscillators that switching speed increases with increasing $\textrm {L}_{{{\textrm {TG}}}}$ for fixed $L$ , verifying that bulk accumulation improves switching speed. However, switching speed drops dramatically when the TG overlaps the source/drain electrodes due to additional parasitic capacitance. TFT-circuits with the longest, but nonoverlapping TGs are demonstrated to exhibit the fastest switching speed; operation frequency exceeding 2.63 MHz for input voltage $\textrm {V}_{{{\textrm {DD}}}}$ of 20 V, which is also the fastest among all inverted staggered amorphous-oxide-semiconductor TFT-based circuits.

High-Performance Solution-Processed InGaZnO Thin-Film Transistor Fabricated by Ozone-Assisted Atmospheric Pressure Mist Deposition

High-performance amorphous indium-gallium–zinc oxide thin-film transistors (IGZO TFTs) were demonstrated at ${\hbox{360}} ^{\circ}{\hbox{C}}$ with the IGZO channel and aluminium oxide (AlOx) gate dielectric stack that was deposited by ozone $({\hbox{O}}_{3})$ -assisted atmospheric pressure chemical vapor deposition (AP-CVD) using an ultrasonic atomized solution mist. The AlOx gate dielectric with a breakdown electric field of over 8 MV/cm and dielectric constant of 7.0 was obtained. In addition, the introduction of ${\hbox{O}}_{3}$ oxidant during the IGZO deposition decreases the carbon and hydrogen contamination in the film. Field effect mobility and the sub-threshold swing of the IGZO TFT with AP-deposited IGZO/AlOx stack were significantly improved to ${\hbox{7.5}}~{\hbox{cm}}^{2} / {\hbox{V}}{\hbox{s}}$ and 0.38 V/dec, respectively, by the ${\hbox{O}}_{3}$ oxidant introduced in the IGZO and AlOx depositions. The ${\hbox{O}}_{3}$ oxidant is very effective in improving the electrical properties of solution-processed oxide TFTs.

Effects of electron trapping and interface state generation on bias stress induced in indium–gallium–zinc oxide thin-film transistors

The electrical characteristics of bias temperature stress (BTS) induced in amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs) were studied. We analyzed the threshold voltage (VTH) shift on the basis of the effects of positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS), and applied it to the stretched-exponential model. Both stress temperature and bias are considered as important factors in the electrical instabilities of a-IGZO TFTs, and the stretched-exponential equation is well fitted to the stress condition. VTH for the drain current–gate voltage (IDS–VGS) curve and flat-band voltage (VFB) for the capacitance–voltage (C–V) curve move in the positive direction when PBTS is induced. However, in the case of NBTS, they move slightly in the negative direction. To clarify the VTH shift phenomenon by electron and hole injection, the average effective energy barrier (Eτ) is extracted, and the extracted values of Eτ under PBTS and NBTS are about 1.33 and 2.25 eV, respectively. The oxide trap charges (Not) of PBTS and NBTS calculated by C–V measurement are 4.4 × 1011 and 1.49 × 1011 cm−2, respectively. On the other hand, the border trap charges of PBTS and NBTS are 6.7 × 108 and 1.7 × 109 cm−2, respectively. This indicates that the increased interface trap charge, after PBTS is induced, captures electrons during detrap processing from the border trap to the conduction band, valence band, and interface trap.

The Dependence of Carrier Distribution on Gate Capacitance of α-IGZO TFTs

The capacitance-voltage (C–V) characteristics of inverted staggered amorphous indium–gallium–zinc-oxide thin film transistors (α-IGZO TFTs) with various dimensions are investigated by physics-based technology computer aided design (TCAD) simulation. For gate bias lower than the threshold voltage of the TFT, the electrons in the channel region are nearly fully depleted. It causes that the total gate capacitance is determined by the overlap region of gate, α-IGZO, and source/drain metals. When the applied gate bias is higher than the threshold voltage, the high electron density channel with density of ~6 × 1017 cm-3 and thickness of ~3-4 nm is observed near the interface of α-IGZO and gate dielectric. It results that the total gate capacitance is dominated by the gate to channel overlap. Quantitative analysis of the carrier distribution and energy band structures are utilized to study the physical mechanism underlying the C–V characteristics of the α-IGZO TFTs.

Investigating electron depletion effect in amorphous indium–gallium–zinc-oxide thin-film transistor with a floating capping metal by technology computer-aided design simulation and leakage reduction

The electron distribution in an amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistor (TFT) with a floating metal–semiconductor (MS) back interface is analyzed using a technology computer-aided design (TCAD) model. The channel geometry (i.e., length and thickness) effect is carefully investigated. At a high work function (i.e., 5 eV) of the capping metal, electrons inside a-IGZO are mostly removed by the capping metal (electron depletion effect). The depletion of the IGZO film leads to an increase in threshold voltage in a-IGZO TFT. TCAD simulation reveals that increasing channel length and decreasing IGZO thickness significantly enhance such an electron depletion effect. Finally, the electron depletion effect is applied to a-IGZO TFT with a high-conductivity IGZO film to greatly suppress the leakage current by over 5 orders.

Low-frequency noise in amorphous indium–gallium–zinc oxide thin-film transistors with an inverse staggered structure and an SiO2 gate insulator

We report the low-frequency noise (LFN) behavior of amorphous indium–gallium–zinc oxide thin-film transistors with an inverse staggered structure and an SiO2 gate insulator. The normalized noise power spectral density depended on channel length, L, with the form 1/L2, and on the gate bias voltage, VG, and threshold voltage, VTH, with the form 1/(VG − VTH)β where 1.5 < β < 2.1. In addition, the scattering constant α was less than 105 Ω. These results suggest that the contact resistance has a significant role in the LFN behavior and the charge-carrier density fluctuation is the dominant origin of LFN.

Investigation of LaAlO 3 /ZrO 2 / a ‐InGaZnO thin‐film transistors using atmospheric pressure plasma jet

Amorphous indium–gallium–zinc-oxide thin-film transistors (a-IGZO-TFTs) with the LaAlO3/ZrO2 gate dielectric stack employing a novel atmospheric pressure plasma jet process that results in small subthreshold swing and low threshold voltage are proposed and fabricated. The influence of post-deposition annealing (PDA) temperature on LaAlO3/ZrO2 gate dielectric stack and device performance was investigated. The equivalent oxide thickness of the LaAlO3/ZrO2 dielectric stack decreases from 11.5 nm without annealing to 7 nm after a 500°C annealing was applied. The LaAlO3/ZrO2/a-InGaZnO TFT with a 500°C annealing exhibits a small subthreshold swing of 77 mV·dec−1, a high field-effect mobility of 9 cm2·V−1·s−1 and an excellent current ratio of 1.8 × 107, which could be attributed to the improved gate dielectric quality by the PDA. The LaAlO3/ZrO2/a-InGaZnO TFTs with excellent gate control ability allow the device to operate at a low operating voltage with low power consumption.

Effect of ${\hbox{SiO}}_{2}$ and/or ${\hbox{SiN}}_{x}$ Passivation Layer on Thermal Stability of Self-Aligned Coplanar Amorphous Indium–Gallium–Zinc–Oxide Thin-Film Transistors

We report the post-annealing effect on the performance of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with self-aligned coplanar structure. The a-IZGO layer was passivated with SiO2 or SiNx by plasma enhanced chemical vapor deposition (PECVD). The field-effect mobility of a-IGZO TFT with SiNx is almost unchanged by extending the post-annealing time at 250 °C, but that of SiO2 passivated TFT significantly degrades by increasing annealing time. It is found that the resistivity of the a-IGZO under SiNx is low enough and thus can be good conduction path, leading to the high performance TFT. It is also found that the interface trap density (Nit) between a-IGZO TFT with SiNx passivation decreases from 3.0×1011 to 1.54×1011 cm-2 eV-1, and the stability of the a-IGZO TFT with SiNx passivation is significantly improved by long post-annealing.

Depth-Profiling Study on Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors by X-ray Photoelectron Spectroscopy

We performed an X-ray photoelectron spectroscopy (XPS) depth-profiling study on the materials used in amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs) with Ti and Mo source/drain (S/D) electrodes. The XPS results suggested that there are some differences between the interface regions of Ti/a-IGZO and Mo/a-IGZO for different chemical states of the materials. The chemical states of the back-channel surfaces were also found to be different between the TFTs with Ti and Mo S/D electrodes. In addition, we fabricated indium–gallium–zinc–titanium oxide composite thin films by deposition using multitarget co-sputtering. The electronic structure of these films observed by XPS is similar to that of the Ti/a-IGZO interface region. The fabricated films were found to have a very low resistivity, much lower than that of an a-IGZO film using typical TFT fabrication processes.

N2O plasma treatment suppressed temperature-dependent sub-threshold leakage current of amorphous indium–gallium–zinc-oxide thin film transistors

N2O plasma treatment suppressed the temperature-dependent sub-threshold leakage current of amorphous indium–gallium–zinc-oxide thin film transistors (a-IGZO TFTs). For untreated devices, the transfer curve exhibited abnormal electrical properties at high temperature. The abnormal electrical properties are explained by the energy band diagrams for both forward and reverse sweep. Above 400K, holes can be generated from trap-assisted transition, and drift to the source side which induces source barrier lowering. The source side barrier lowering enhances electron injection from the source to channel and causes an apparent sub-threshold leakage current. This phenomenon, which is experimentally verified, only appears in the device without N2O plasma treatment, but not in the device with N2O plasma treatment. The results suggested that the density of states for a-IGZO with N2O plasma treatment is much lower than that without plasma treatment.

Amorphous indium–gallium–zinc oxide thin-film transistors instability and stress evaluation by Stretched-Exponential model

We have successfully fabricated large sized amorphous indium–gallium–zinc-oxide based active-matrix liquid-crystal displays, which uses Molybdenum/Aluminum/Titanium as source/drain electrode. In this study, an oxygen-rich etch stop layer acts as the oxygen atom supplier and converts the titanium layer into titanium oxide layer, which is found to induce instability of the device. Sample without titanium oxide has an initial threshold voltage shift is less than ±0.1V after the repeatedly measuring over a period of two weeks. In addition, the IGZO based device demonstrated superior transfer characteristic. This paper established that the stability of the amorphous indium–gallium–zinc-oxide based active-matrix liquid-crystal display can be predicted by Stretched-Exponential model.

Migration of indium ions in amorphous indium–gallium–zinc-oxide thin film transistors

Electromigration of In in amorphous indium–gallium–zinc-oxide thin film transistors under repeated switching operation was investigated by analyzing the distribution of component elements. During the repeated switching operations up to 300 times, threshold voltage of this device increased gradually implying alteration to the internal device structures. Energy dispersive X-ray spectroscopy revealed noticeable redistribution of metallic components, especially In, in the channel layer beneath the source electrode during switching operations by the migration of metallic ions away from the source electrode, which is attributed to electromigrations similar to those observed in organic light emitting diodes having indium tin oxide electrodes.

Effect of annealing time on bias stress and light-induced instabilities in amorphous indium–gallium–zinc-oxide thin-film transistors

Thermal post annealing was employed for amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs) to optimize performance by a low-temperature process, in view of the envisaged role of a-IGZO in plastic electronics. The effect of annealing time at T = 250 and 280 °C on bias stress and light-induced instabilities was investigated. We find that long anneals are effective in reducing bias stress and light-induced instabilities, as well as hysteresis in the transfer characteristics. The time constant τ for positive bias stress and for negative bias stress increases after long anneal, attaining for positive bias stress the value of 1.05 × 106 s, the highest so far reported for these devices. The beneficial effect of long anneals appears to be because of a reorganization of the amorphous network, resulting in a more stable configuration.

Electrical Properties and Stability of Dual-Gate Coplanar Homojunction DC Sputtered Amorphous Indium–Gallium–Zinc–Oxide Thin-Film Transistors and Its Application to AM-OLEDs

The electrical characteristics and stability of dual-gate (DG) coplanar homojunction amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) on glass substrates are described herein. In this device structure, both top gate (TG) and bottom gate are defined by lithography, allowing independent biasing when adjacent TFTs are present. The DG a-IGZO TFT demonstrates excellent electrical performance with subthreshold swing (SS) of 99 mV/dec, field-effect mobility of 15.1 , and on- off current ratio of . By applying various bias voltages on the TG electrode, it is found that the TFT threshold voltage can be controlled without any change of the SS and off current. Under conditions of negative bias temperature stress (BTS), the transfer curves of the TFT exhibit negligible shifts after 10 000 s. Larger shifts are observed under conditions of a positive BTS. Finally, the application of this DG device to active-matrix organic light-emitting displays is suggested.

Effect of magnesium oxide passivation on the performance of amorphous indium–gallium–zinc-oxide thin film transistors

Effect of hygroscopic magnesium oxide (MgO) passivation layer on the stability of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under positive bias stress and positive bias temperature stress has been investigated. The effect of MgO passivation has been observed by comparing the shift of the positive threshold voltage (Vth) after constant bias temperature stress, which were 8.2V for the unpassivated TFTs and 1.88V for the passivated TFTs.In addition, MgO passivated a-IGZO TFTs show also excellent stability under a humidity test since MgO passivation layer can prevent the penetration of water into back channel. In order to investigate the origin of humidity test result, we have measured X-ray photoelectron spectroscopy depth profile of both unpassivated and MgO passivated TFTs with a-IGZO back channel layers after N2 wet annealing.

Paraffin wax passivation layer improvements in electrical characteristics of bottom gate amorphous indium–gallium–zinc oxide thin-film transistors

In this research, paraffin wax is employed as the passivation layer of the bottom gate amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs), and it is formed by sol–gel process in the atmosphere. The high yield and low cost passivation layer of sol–gel process technology has attracted much attention for current flat-panel-display manufacturing. Comparing with passivation-free a-IGZO TFTs, passivated devices exhibit a superior stability against positive gate bias stress in different ambient gas, demonstrating that paraffin wax shows gas-resisting characteristics for a-IGZO TFTs application. Furthermore, light-induced stretch-out phenomenon for paraffin wax passivated device is suppressed. This superior stability of the passivated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities.

Empirical Modeling and Extraction of Parasitic Resistance in Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors

We propose an extraction technique for parasitic resistance (RP) with L-, VGS-, and VDS-dependences even for large VDS in amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs), by employing IDS-VGS characteristics (as a function of VDS ) of two a-IGZO TFTs with different channel lengths ( L1 and L2 ). The resistance between the source and drain is modeled as an effective total resistance defined as RT* ≡ VDS/ID for all over the drain bias VDS including both linear and saturation regions. The proposed method can be efficiently employed to model dc I-V characteristics and extract the parasitic resistance in a-IGZO TFTs even with short channel lengths, because the internal drain voltage (VDS') is accurately calculated as a function of VGS, VDS, and L by deembedding the voltage drop across the parasitic resistance RP.

Extraction of Separated Source and Drain Resistances in Amorphous Indium–Gallium–Zinc Oxide TFTs Through $C$– $V$ Characterization

Considering asymmetry caused by layout, process, and device degradation, separate extraction of the source and drain resistances, i.e., <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RS</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RD</i> , respectively, from the total resistance <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TOT</sub> is very important in the design, modeling, and characterization of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). Due to the insulated gate structure, however, separate extraction is difficult through direct-current <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characterization. In this letter, we propose a simple and useful technique for separate extraction of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RS</i> from <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RD</i> in a-IGZO TFTs through a two-terminal parallel-mode <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> technique. We experimentally verified the validity of the proposed technique by comparing the result with the source-to-drain resistance from the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics.

Inverters Using Only N-Type Indium Gallium Zinc Oxide Thin Film Transistors for Flat Panel Display Applications

Two inverter architectures are proposed to be integrated on panels for flat panel display applications using only n-type amorphous indium gallium zinc oxide (IGZO) thin film transistors (TFTs). The proposed cross-coupled (CC) inverter uses the positive feedback effect of its CC structure to reduce the static current and increase the output voltage swing when using depletion mode n-type amorphous IGZO TFTs. The other proposed cross-coupled and bootstrapping (CCB) inverter also uses the cross-coupled structure and includes a capacitor for the bootstrapping effect to increase the operating frequency. The measured results show that the output voltage swing of the proposed CC inverter is from 0 to 14.50 V and that of the CCB inverter is from 0.15 to 14.57 V when VDD is 15 V at 20 kHz and the load capacitance is 103.0 pF. The power consumption of the CC and CCB inverters are 1.4 and 2.5 mW, respectively, which are 29.3 and 53.4% of the power consumption of the ratioed inverter.