Ambipolar Current Research Articles

A high-performance p-type based heterostructure electrically doped NTFET and representation of a neural network model

This paper presents an electrically doped N-type Tunnel FET(ED-NTFET) using P+ substrate wherein gate electrodes (polarity and control) with the same work function are employed over the gate oxide. Then a positive fixed voltage is applied to polarity gate to accumulate N+ drain. Furthermore, Ge with a narrow band gap is used as the source material and GaAs as the channel and drain materials to realize a heterostructure channel/source interface which improves on state current and ambipolar behavior. To suppress ambipolar current, a metal is implanted in the gate oxide at the drain/channel junction which increases the tunnel barrier width at this junction. Additionally, optimized metal length is extracted based on trading off between the higher on state current and the lower ambipolar current. Significant electrical characteristics of the device demonstrate that it can be an appropriate candidate for analog and digital applications. In the following, an ED NTFET model based on perceptron artificial neural network is presented which can accurately predict the drain current for various physical and electrical parameters such as the gate work function, the oxide thickness, the gate voltage, and the drain voltage. The model can be implemented for more parameters and also used as a device simulator.

Impact of interface traps on performance of Gate-on-Source/Channel SOI TFET

Here, one of most important reliability issue of the semiconductor device, the effects of traps present at the oxide-semiconductor interfaces on gate-on-source/channel SOI TFET are investigated. Conventional SOI TFET, gate-on-source only TFET, and gate-on-source/channel TFET are compared and it is found that gate-on-source/channel TFET has better immunity to the interface trap charge variation. The gate-on-source/channel TFET exhibits higher on current and on-off current ratio than gate-on-source device. Preliminary analyses are presented for the proposed architecture for the parameters: gate-channel overlap, back gate voltage and buried oxide thickness in absence of interface traps. The back gate voltage has a significant effect on the channel-drain junction of the device, and hence, on the ambipolar current. Further, the device characteristics in presence of traps at the gate oxide-semiconductor interface and buried oxide-semiconductor interface are reported. The effect of trap concentration is observed on the transfer characteristics, capacitance, and cut off frequency. The front gate dielectric-semiconductor interface traps degrade on current, while the buried oxide-semiconductor interface traps affect the ambipolar current. The effect of back gate voltage on ambipolarity and on current of the proposed device is studied in detail in presence of traps.

First Principles Study of the Ambipolarity in a Germanene Nanoribbon Tunneling Field Effect Transistor

In this article, the effects of hetero-dielectric gate material and gate-drain underlap on the ambipolar and ON-state current of a germanene nanoribbon (GeNR) tunneling field-effect transistors (TFETs) is examined. The simulations are performed using the combination of density functional theory (DFT) and non-equilibrium Green's function (NEGF) formalism. It was observed that using high-k dielectric gate material increases the ON-state current while the combination of hetero-dielectric gate material and gate-drain underlap suppresses the ambipolar current and improves the ON-state current. In addition, the effect of various hetero-junctions in the source region on the performance of GeNR-TFET was investigated. Due to the dependency between the width and energy bandgap in GeNR, utilizing a small bandgap in the source improves ON-state current and its ambipolar behavior.

Representation of heterostructure electrically doped nanoscale tunnel FET with Gaussian-doping profile for high-performance low-power applications

In this paper, a gallium antimonide junctionless tunnel field-effect transistor based on electrically doped concept (GaSb–EDTFET) is studied and simulated. The performance of the device is analyzed based on the energy band diagram and electric field profile. The on-current, transconductance, and cut-off frequency are enhanced in case of GaSb–EDTFET compared with Si-EDTFET due to the combination of the high tunneling efficiency of the narrow bandgap and the high-electron mobility of GaSb. On the other hand, the Gaussian-doping profile decreases the ambipolar and off current by increasing the tunneling barrier length at the drain/channel interface. Hence, applying Gaussian-doping profile on GaSb–EDTFET makes it a suitable candidate for analog and digital applications. Next, heterostructure channel/source interface EDTFET is studied which uses GaSb for the source and AlGaSb for the drain and channel regions. Then, it has been optimized by numerical simulation in terms of aluminum (Al) composition. The optimal Al composition was founded to be around 10% (x = 0.1). It is shown that the blend of Gaussian-doping profile and the heterostructure channel/source interface with optimal Al composition remarkably reduces ambipolar current amount to a value of 1.3 × 10−23 A/μm. The improvements in terms of Ioff, Ion, Ion/Ioff rate, subthreshold swing, transconductance, cut-off frequency, and also suppressed ambipolar behavior are illustrated by numerical simulations.

Impact of leakage current in germanium channel based DMDG TFET using drain-gate underlap technique

In this work, a dual metal (DM) double-gate (DG) Tunnel Field Effect Transistor (DMDG-TFET) with drain-gate underlap is proposed to overcome the challenges in conventional TFET. The ON-current (Ion), OFF-current (Ioff), Ion/Ioff ratio, subthreshold swing (SS) and ambipolar current (Iambi) of the proposed device with drain underlap are investigated as gate length is scaled (LGATE) down. The proposed device gives a better suppression in leakage current and low ambipolar current. The suppressed leakage current (Ioff) and ambipolar current (Iambi) are 9.49 × 10−14 A/µm and 1.95 × 10−12 A/µm respectively for a gate length (LGATE) of 36 nm and a channel length (LCh) of 50 nm for a supply voltage of 0.5 V. Excellent switching behavior is achieved when gate length (LGATE) is 72% of the channel length (LCh). The proposed architecture is suitable for low power applications.

Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications

This paper investigates the performance of tri material gate tunnel field effect transistor (TMGTFET) device designed in gate all around (GAA) configuration. The device performance is analyzed by varying various device related parameters like: drain doping, oxide thickness and radius of silicon core. Simulations are performed using technology computer-aided design (TCAD) tool at 60 nm gate length. Simulation results show that the performance of TMGTFET device can be optimized by proper selection of device parameters so as to achieve improvements in the ON current, OFF current, sub-threshold swing and ambipolar current. The silicon based TMGTFET device demonstrates good performance which makes it a suitable candidate for low power applications with ON current of 0.386 µA/µm, average sub-threshold swing of 32.06 mV/decade, maximum current gain cut off frequency of 41.4 GHz and extremely low OFF current value of the order of 10-20A/µm. We have performed the device optimization to boost the ON current and improve the sub-threshold slope in order to make sure that this device configuration becomes suitable for both low power and high performance applications. The proposed hetero dielectric tri material gate tunnel FET device (HD-TFET) designed in gate all around configuration achieves 19.7 times improvement in ON current as compared to TMGTFET device and excellent average sub-threshold swing of 21.2 mV/decade. The maximum unity current gain frequency is also improved by 3 times indicating its potential for deployment in high frequency applications.

Work-Function Engineering of Source-Overlapped Dual-Gate Tunnel Field-Effect Transistor.

A source-overlapped dual-material gate TFET (SODM-TFET), which features different materials in its source-overlapped and channel gates, is proposed here, and its performance is investigated for various channel and source gate work functions (ψmc and ψms, respectively). Previous studies reported a hump effect in source-overlapped TFETs (SO-TFETs) and relatively high currents in the ambipolar state. The flat-band voltage in our SODM-TFET was controlled by modulating ψms and ψmc, allowing to reduce the hump effect and suppressing the ambipolar current. Compared with conventional SO-TFETs, minimal subthreshold-swing (SSmin) and average SS (SSavg) of our SODM-TFET were ~4 and ~3.5 times lower, respectively. The on/off current ratio (Ion/Ioff) of the SODM-TFET increased by ~100, while the on-current (Ion) of the SODM-TFET increased by ~100 at the supply voltage of 0.7 V.

Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET

An analytical model was developed to calculate the potential distribution for a gate-underlap double-gate tunnel FET. The electrostatic potential of the device was derived using the two-dimensional Poisson’s equation, incorporating the fringing electric field in the gate-underlap surface and employing a conformal mapping method. In addition to analytical potential modeling, the electric field and drain current were evaluated to investigate the device performance. Excellent agreement with technology computer-aided design (TCAD) simulation results was observed. The dependence of the ambipolar current on the spacer oxide dielectric constant, spacer length, channel length, and gate material thickness was examined using the proposed model. The effects of the variation of all of these parameters were well predicted, and the model reveals that use of a low- $$\kappa $$ spacer dielectric combined with a high- $$\kappa $$ gate dielectric results in the minimal ambipolar current for the device.

Workfunction Engineering of A Pocket Tunnel Field-Effect Transistor with A Dual Material Gate

A dual-material gate pocket tunnel field-effect transistor (DM-PTFET) with separated source gate and channel gate materials is newly proposed. As the workfunctions of the source and the channel gates in the DM-PTFET were varied, we investigated systematically the optimal workfunction region where the hump effect was removed and the ambipolar current was minimized. Also, we investigated the optimal workfunctions of the dual-material gates in the DM-PTFET for three pocket thickness, Tpocket = 1, 2, and 3 nm. The highest on-current Ion was observed when Tpocket = 1.5 nm, and the off-current Ioff decreased as the Tpocket was increased, and the optimal Tpocket is 2 nm in terms of Ion/Ioff ratio. The band-to-band tunneling (BTBT), which occurs in the gate-pocket direction in the source, was affected by the source gate, and the BTBT, which occurs in the channel direction in the source, was affected by the channel gate. The hump effect was removed when the work functions of the source gate were 0.05, 0.16, and 0.26 eV less than that of the channel gate when the Tpocket = 1, 2, and 3 nm, respectively. In the optimal structure of the DM-PTFET (with no hump effect, Tpocket = 2 nm, and workfunction of the channel gate < 3.7 eV), Iambipolar decreased by 104 times compared to its value for a conventional PTFET.

Ge/Si heterojunction L-shape tunnel field-effect transistors with hetero-gate-dielectric**Project supported by the National Natural Science Foundation of China (Grant Nos. 61574109 and 61204092).

A Ge/Si heterojunction L-shaped tunnel field-effect transistor combined with hetero-gate-dielectric (GHL-TFET) is proposed and investigated by TCAD simulation. Current–voltage characteristics, energy-band diagrams, and the distribution of the band-to-band tunneling (BTBT) generation rate of GHL-TFET are analyzed. In addition, the effect of the vertical channel width on the ON-current is studied and the thickness of the gate dielectric is optimized for better suppression of ambipolar current. Moreover, analog/RF figure-of-merits of GHL-TFET are also investigated in terms of the cut-off frequency and gain bandwidth production. Simulation results indicate that the ON-current of GHL-TFET is increased by about three orders of magnitude compared with that of the conventional L-shaped TFET. Besides, the introduction of the hetero-gate-dielectric not only suppresses the ambipolar current effectively but also improves the analog/RF performance drastically. It is demonstrated that the maximum cut-off frequency of GHL-TFET is about 160 GHz, which is 20 times higher than that of the conventional L-shaped TFET.

Impact of Biosensor Permittivity on a Double-Gate nTFET Ambipolar Current

Biosensors are defined as any device that senses and transmits information about a biological element. The importance of biosensors for health and environment monitoring increase in the past decades, due the global warming, pollution and new biological pathogens. In order to achieve better sensing and to scale down the device dimensions and other advantages (1), the use of field effect transistors (FETs) as biosensors have been studied recently. The goal of this work is to analyze the effect of gate to drain underlapping on n-type Tunnel-FET (nTFET) devices, filled with different dielectric permittivity material (k) in order to simulate the bio element materials. The gate length (LG, where LG = 50nm – LU) was studied changing the underlap (LU) for a range of 0nm (self-aligned) to 15 nm of underlap, with step of 5 nm. The total channel length (LSD, where LSD = 50nm +LU) was evaluated fixing the LG=50 nm and adding the underlap part. In all cases, different dielectric permittivity (k) was considered in these analysis as the bio element. The structure of the Double Gate DG-nTFET biosensor is shown in Fig.1. The parameters used for simulation are: silicon film thickness, tSi = 10 nm, equivalent oxide thickness EOT = 1 nm, channel length LSD = 50 nm, thickness of the bio element tBio = 10 nm and the length of the drain and source regions LD = LS = 100 nm. The gate (Titanium Nitride) work function = 4.7 eV, source doping NA =1.1020 cm-3, drain doping ND= 1.1020 cm-3 and channel doping ND = 1.107 cm-3 . The models used are nonlocal band-to-band tunneling (BTBT), Shockley-Read-Hall (SRH) recombination and band-gap narrowing (BGN) model. The transfer curve of nTFETs with different underlap values are shown in Fig.2. It is observed that with the increment of LU the TFET ambipolar current (drain to channel tunneling) decreases, as already reported in (2). However, if the k values increase, the ambipolar currents increase as can be seen in Fig.3. This effect can be explained in Fig.4, where it is possible to see that the tunneling length becomes thinner when K raise due to improvement of the tunneling between drain and channel. In order to analyze a better configuration for a biosensor device, a sensitivity parameter defined as Sensivity = ID(K=n)/ID(k=1), where n is the value of the corresponding k, was used for comparing all different type of configurations studied in this paper. The sensitivity increases with the k value and with different LU is shown in Fig.5. The best sensitivity is obtained for high K and high underlap region. In the case of the device with LG fixed at 50 nm, the Fig.6 shows that the sensitivity increases with k and the highest sensitivity was obtained for lower underlap (5 nm). It can be explained analyzing the band diagram of the Fig.7, where it is possible to notice that the tunnel length decreases for lower underlap region. An investigation of the impact of biosensor permittivity on a DG-nTFET ambipolar current was done. The bio elements detection using the underlap region showed high sensitivity, of orders of magnitude for different LU and k values. The highest sensitivity for an nTFET biosensor was observed for a Lu = 15 nm (higher Lu), LSD = 50nm (smaller LSD) and higher k bio element, in the range studied in this paper. Figure 1

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high-k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

Optimization of L-shaped tunneling field-effect transistor for ambipolar current suppression and Analog/RF performance enhancement

L-shaped tunneling field-effect transistor (LTFET) has larger tunnel area than planar TFET, which leads to enhanced on-current ION. However, LTFET suffers from severe ambipolar behavior, which needs to be further optimized for low power and high-frequency applications. In this paper, both hetero-gate-dielectric (HGD) and lightly doped drain (LDD) structures are introduced into LTFET for suppression of ambipolarity and improvement of analog/RF performance of LTFET. Current-voltage characteristics, the variation of energy band diagrams, distribution of band-to-band tunneling (BTBT) generation and distribution of electric field are analyzed for our proposed HGD-LDD-LTFET. In addition, the effect of LDD on the ambipolar behavior of LTFET is investigated, the length and doping concentration of LDD is also optimized for better suppression of ambipolar current. Finally, analog/RF performance of HGD-LDD-LTFET are studied in terms of gate-source capacitance, gate-drain capacitance, cut-off frequency, and gain bandwidth production. TCAD simulation results show that HGD-LDD-LTFET not only drastically suppresses ambipolar current but also improves analog/RF performance compared with conventional LTFET.

Charge plasma based source/drain engineered Schottky Barrier MOSFET: Ambipolar suppression and improvement of the RF performance

This paper reports a novel device structure for charge plasma based Schottky Barrier (SB) MOSFET on ultrathin SOI to suppress the ambipolar leakage current and improvement of the radio frequency (RF) performance. In the proposed device, we employ dual material for the source and drain formation. Therefore, source/drain is divided into two parts as main source/drain and source/drain extension. Erbium silicide (ErSi1.7) is used as main source/drain material and Hafnium metal is used as source/drain extension material. The source extension induces the electron plasma in the ultrathin SOI body resulting reduction of SB width at the source side. Similarly, drain extension also induces the electron plasma at the drain side. This significantly increases the SB width due to increased depletion at the drain end. As a result, the ambipolar leakage current can be suppressed. In addition, drain extension also reduces the parasitic capacitances of the proposed device to improve the RF performance. The optimization of length and work function of metal used in the drain extension is performed to achieve improvement in device performance. Moreover, the proposed device makes fabrication simpler, requires low thermal budget and free from random dopant fluctuations.

Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis

In this paper, we investigate the impact of a drain-pocket (DP) adjacent to the drain region in Tunnel Field-Effect Transistors (TFETs) to effectively suppress the ambipolar current. Using calibrated two-dimensional device simulation, we examine the impact of DP in Double Gate TFET (DGTFET). We demonstrate the superiority of the DP technique over the existing techniques in controlling the ambipolar current. In particular, the addition of DP to a TFET is able to fully suppress the ambipolar current even when TFET is biased at high negative gate voltages and drain doping is kept as high as the source doping. Moreover, adding DP is complementary to the well-known technique of employ-ing source-pocket (SP) in a TFET since both need similar doping type and doping concentration.

Impact of low/high-κ spacer–source overlap on characteristics of tunnel dielectric based tunnel field-effect transistor

The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor (TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling (BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel (or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si3N4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope (S S) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.

Performance improvement of doped TFET by using plasma formation concept

Formation of abrupt doping profile at tunneling junction for the nanoscale tunnel field effect transistor (TFET) is a critical issue for attaining improved electrical behaviour. The realization of abrupt doping profile is more difficult in the case of physically doped TFETs due to material solubility limit. In this concern, we propose a novel design of TFET. For this, P+ (source)-I (channel)-N (drain) type structure has been considered, wherein a metal electrode is deposited over the source region. In addition to this, a negative voltage is applied to the source electrode (SE). It induces the surface plasma layer of holes in the source region, which is responsible for steepness in the bands at source/channel junction and provides the advantage of higher doping in source region without any addition of the physical impurity. The proposed modification is helpful for achieving steeper band bending at the source/channel interface, which enables higher tunneling generation rate of charge carriers at this interface and overcomes the issue of low ON-state current. Thus, the proposed device shows the increment of 2 decades in drain current and 252 mV reduction in threshold voltage compared with conventional device. The optimization of spacer length (LSG) between source/gate (LSG) and applied negative voltage (Vpg) over source electrode have been performed to obtain optimum drain current and threshold voltage (Vth). Further, for the suppression of ambipolar current, drain region is kept lightly doped, which reduces the ambipolar current up to level of Off state current. Moreover, in the proposed device gate electrode is underlapped for improving RF performance. It also reduces gate to drain capacitances (Cgd) and increases cut-off-frequency (fT), fmax, GBP, TFP. In addition to these, linearity analysis has been performed to validate the applicability of the device.

Gate engineered heterostructure junctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement

This study investigates a junctionless tunnel field-effect transistor with a dual material gate and a heterostructure channel/source interface (DMG-H-JLTFET). We find that using the heterostructure interface improves device behavior by reducing the tunneling barrier width at the channel/source interface. Simultaneously, the dual material gate structure decreases ambipolar current by increasing the tunneling barrier width at the drain/channel interface. The performance of the device is analyzed based on the energy band diagram at on, off, and ambipolar states. Numerical simulations demonstrate improvements in ION, IOFF, ION/IOFF, subthreshold slope (SS), transconductance and cut-off frequency and suppressed ambipolar behavior. Next, the workfunction optimization of dual material gate is studied. It is found that if appropriate workfunctions are selected for tunnel and auxiliary gates, the JLTFET exhibits considerably improved performance. We then study the influence of Gaussian doping distribution at the drain and the channel on the ambipolar performance of the device and find that a Gaussian doping profile and a dual material gate structure remarkably reduce ambipolar current. Gaussian doped DMG-H-JLTFET, also exhibits enhanced IOFF, ION/IOFF, SS and a low threshold voltage without degrading IOFF.

Controlling ambipolarity with improved RF performance by drain/gate work function engineering and using high $$\kappa $$ κ dielectric material in electrically doped TFET: proposal and optimization

This article proposes a novel device structure of electrically doped tunnel FET with drain/gate work function engineering by using hetero-dielectric material for the suppression of ambipolar behavior with improved DC and RF characteristics. For this, a P–I–N type structure was formed over an intrinsic silicon wafer by applying negative and positive voltages to create source and drain regions, respectively. Formation of source and drain regions by the concept of electrical doping is useful for reduction of random doping fluctuations and fabrication complexity. For suppression of ambipolar behaviour, the drain electrode is split into two different metal work functions ( $$\phi _\mathrm{DE1}$$ < $$\phi _\mathrm{DE2}$$ ), which alters the carrier concentration and increases the tunneling barrier at the drain/channel interface. Consequently, the proposed modification in terms of dual work functionality at the drain terminal offers better performance in terms of suppression of negative conductance (ambipolar current) and parasitic capacitances. However, the presence of dual work functionality at the drain electrode causes degradation in ON-state current and RF figures of merit. To resolve these problems, the control gate electrode is further split into two different work functions and uses hetero gate dielectric material, where the gate work function near the source/channel interface is greater than the gate work function near the drain/channel interface. It assists tunneling of carriers at the source/channel junction and improves ON-state current with RF performance. Apart from this, the use of hetero gate dielectric material provides further enhancement in DC and high frequency behaviour of the device.

A novel electrostatically doped ferroelectric Schottky barrier tunnel FET: process resilient design

This work investigates a process-variation resilient electrostatically-doped ferroelectric Schottky-barrier tunnel FET (ED-FE-SB-TFET) based on negative capacitance (NC). The key attributes of ED-FE-SB-TFET are perovskite ferroelectric (FE) gate stack-induced NC behavior and electrostatic doping to induce pockets at both source/drain and channel interfaces. The positive feedback among the electric dipoles in FE material leads to intrinsic voltage amplification and enhanced gate controllability, thus it facilitates faster switching transitions. The proposed ED-FE-SB-TFET endeavors to create a substantial reduction in the ambipolar current ( $$I_\mathrm{Amb}$$ ), steep sub-threshold slope, paramount boost in drive current, lower drain-induced barrier-lowering, and enhanced scalability. It also obviates the need for metallurgical doping, hence ion-implantation or dopant segregation techniques employed for planar SB-TFETs pocket-doping are no longer required, and it also modifies effective Schottky barrier height and Schottky tunneling barrier width significantly to enhance the device behavior. It offers a simplified fabrication process, and it is highly resilient towards process variations, doping control issues, and random dopant fluctuations. Moreover, there is a reduced thermal budget that facilitates its fabrication on single crystal silicon-on-glass substrate realized by wafer scale epitaxial transfer. Results reveal its potential as strong candidate for next generation, scaled and low power applications.