Alternative Channel Materials Research Articles

Innovations of metallic contacts on semiconducting 2D transition metal dichalcogenides toward advanced 3D-structured field-effect transistors.

2D semiconductors, represented by transition metal dichalcogenides (TMDs), have the potential to be alternative channel materials for advanced 3D field-effect transistors, such as gate-all-around field-effect-transistors (GAAFETs) and complementary field-effect-transistors (C-FETs), due to their inherent atomic thinness, moderate mobility, and short scaling lengths. However, 2D semiconductors encounter several technological challenges, especially the high contact resistance issue between 2D semiconductors and metals. This review provides a comprehensive overview of the high contact resistance issue in 2D semiconductors, including its physical background and the efforts to address it, with respect to their applicability to GAAFET structures.

Sub-5 nm Gate-Length Monolayer Selenene Transistors.

Two-dimensional (2D) semiconductors are being considered as alternative channel materials as silicon-based field-effect transistors (FETs) have reached their scaling limits. Recently, air-stable 2D selenium nanosheet FETs with a gate length of 5 µm were experimentally produced. In this study, we used an ab initio quantum transport approach to simulate sub-5 nm gate-length double-gate monolayer (ML) selenene FETs. When considering negative-capacitance technology and underlap, we found that 3 nm gate-length p-type ML selenene FETs can meet the 2013 ITRS standards for high-performance applications along the armchair and zigzag directions in the 2028 horizon. Therefore, ML selenene has the potential to be a channel material that can scale Moore's law down to a gate length of 3 nm.

Scaling limits of monolayer AlN and GaN MOSFETs

The shrinking of transistors to ultra-scale limits is in great demand to extend Moore’s law, where the search for proper alternative channel materials is significant. The III-V group compounds are regarded as post-Si candidates for their high electron mobility. Herein, we simulate the monolayer (ML) AlN and GaN metal–oxidesemiconductor field-effect transistors (MOSFETs) with ab initio quantum transport simulation to evaluate their scale limit. The ML AlN and GaN MOSFETs exhibit much better n-type performances than their p-type counterparts, and the n-type ML AlN (GaN) MOSFETs can surpass the International Roadmap for Device and Systems (IRDS, 2022 version) lower-power (LP) and high-performance (HP) target for the year 2028 even at gate length (Lg) of 3 and 2 nm, respectively. Encouragingly, the optimal n-type ML AlN (GaN) MOSFETs possess the highest (second-highest) Ion against all studied n-type ML MOSFETs and propel the Lg limit that outperforms the International Technology Roadmap for Semiconductors (ITRS, 2013 version) LP and HP targets to 2 and 1 (2) nm, respectively.

Device Performance of Double-Gate Schottky-Barrier Graphene Nanoribbon Field-Effect Transistors with Physical Scaling

Moore’s law is approaching its limit due to various challenges, especially the size limit of the transistors. The International Roadmap for Devices and Systems (IRDS), the successor of International Technology Roadmap for Semiconductors (ITRS), has included 2D materials as an alternative approach for the More-than-Moore nanoelectronic applications. Among the 2D materials, graphene nanoribbons (GNRs) have been widely used as the alternative channel materials of field-effect transistors (FETs). In this paper, the impacts of physical scaling on the device performance of double-gate Schottky-barrier GNR FETs (DG-SB-GNRFETs) are investigated by using NanoTCAD ViDES simulation tool based on the tight-binding Hamiltonian and self-consistent solutions of 3D Poisson and Schrödinger equations with open boundary conditions within the nonequilibrium Green’s function formalism. The extracted device performance parameters include the subthreshold swing and on-to-off current ratio. The results suggest that the performances of DG-SB-GNRFETs are strongly dependent on their physical parameters, especially the widths of the GNRs.

Systematic investigation of the mechanical, electronic, and interfacial properties of high mobility monolayer InAs from first-principles calculations.

Due to the excellent electrostatic control, high mobility, large specific surface area, and suitable direct energy gap of two-dimensional (2D) indium arsenide (InAs), it is regarded as one of the most promising alternative channel materials for next-generation electronic and optoelectronic devices. Recently, 2D semiconducting InAs has been successfully prepared. Based on first-principles calculations, we calculate the mechanical, electronic, and interfacial properties of monolayer (ML) fully-hydrogen-passivated InAs (InAsH2) material. The results show that 2D InAsH2 with excellent stability has a suitable logic device band gap (1.59 eV) comparable to silicon (1.14 eV) and 2D MoS2 (1.80 eV), and the electron carrier mobility of ML InAsH2 (490 cm2 V-1 s-1) is twice as large as that of 2D MoS2 (200 cm2 V-1 s-1). In addition, we study the electronic structure of the interfacial contact characteristics of ML half-hydrogen-passivated InAs (InAsH) with seven bulk metals (Ag, Au, Cu, Al, Ni, Pd, Pt) and two 2D metals (ML Ti2C and ML graphene). 2D InAs was metallized after contact with the seven bulk metals and two 2D metals. Based on the above, we insert 2D boron nitride (BN) between ML InAsH and the seven low/high-power function bulk metals to eliminate the interfacial states. Remarkably, the semiconducting properties of 2D InAs with Pd and Pt electrodes are recovered, and 2D InAs achieves p-type ohmic contact with the Pt electrode, which facilitates high on-current and high-frequency operation of the transistor. Hence, this work provides systematic theoretical guidance for the design of next-generation electronic devices.

Nanometer-Thick Oxide Semiconductor Transistor with Ultra-High Drain Current.

High drive current is a critical performance parameter in semiconductor devices for high-speed, low-power logic applications or high-efficiency, high-power, high-speed radio frequency (RF) analogue applications. In this work, we demonstrate an In2O3 transistor grown by atomic layer deposition (ALD) at back-end-of-line (BEOL) compatible temperatures with a record high drain current in planar FET, exceeding 10 A/mm, the performance of which is 2-3 times better than all known transistors with semiconductor channels. A high transconductance reaches 4 S/mm, recorded among all transistors with a planar structure. Planar FETs working ballistically or quasi-ballistically are exploited as one of the simplest platforms to investigate the intrinsic transport properties. It is found experimentally and theoretically that a high carrier density and high electron velocity both contribute to this high on-state performance in ALD In2O3 transistors, which is made possible by the high-quality oxide/oxide interface, the metal-like charge-neutrality-level (CNL) alignment, and the high band velocities induced by the low density-of-state (DOS). Experimental Hall, I-V, and split C-V measurements at room temperature confirm a high carrier density of up to 6-7 × 1013 /cm2 and a high velocity of about 107 cm/s, well-supported by density functional theory (DFT) calculations. The simultaneous demonstration of such high carrier concentration and average band velocity is enabled by the exploitation of the ultrafast pulse scheme and heat dissipation engineering.

High-Performance Thin-Film Transistor with Atomic Layer Deposition (ALD)-Derived Indium-Gallium Oxide Channel for Back-End-of-Line Compatible Transistor Applications: Cation Combinatorial Approach.

In this paper, the feasibility of an indium-gallium oxide (In2(1-x)Ga2xOy) film through combinatorial atomic layer deposition (ALD) as an alternative channel material for back-end-of-line (BEOL) compatible transistor applications is studied. The microstructure of random polycrystalline In2Oy with a bixbyite structure was converted to the amorphous phase of In2(1-x)Ga2xOy film under thermal annealing at 400 °C when the fraction of Ga is ≥29 at. %. In contrast, the enhancement in the orientation of the (222) face and subsequent grain size was observed for the In1.60Ga0.40Oy film with the intermediate Ga fraction of 20 at. %. The suitability as a channel layer was tested on the 10-nm-thick HfO2 gate oxide where the natural length was designed to meet the requirement of short channel devices with a smaller gate length (<100 nm). The In1.60Ga0.40Oy thin-film transistors (TFTs) exhibited the high field-effect mobility (μFE) of 71.27 ± 0.98 cm2/(V s), low subthreshold gate swing (SS) of 74.4 mV/decade, threshold voltage (VTH) of -0.3 V, and ION/OFF ratio of >108, which would be applicable to the logic devices such as peripheral circuit of heterogeneous DRAM. The in-depth origin for this promising performance was discussed in detail, based on physical, optical, and chemical analysis.

(Digital Presentation) Scalable Growth of Transition Metal Dichalcogenides for Next-Generation Nanoelectronics

Alternative channel materials for future ultra-scaled electronic devices have been intensively pursued nowadays since the feature size of silicon-based transistors has been scaled down to their physical limit. Atomically-thin semiconducting transitional metal dichalcogenides (TMDCs) including WS2, MoS2, WSe2, MoSe2, e. have shown a lot of unique properties compared to their bulk crystals, such as indirect-to-direct bandgap transitions, strong spin-orbit coupling and valley polarization. In particular, monolayer WS2 has shown the highest theoretical room temperature electron mobility among other semiconducting TMDCs as a result of its low effective mass. Combined with the large exciton/trion binding energy with high photoluminescence quantum yield, monolayer WS2 is a strong candidate as a potential channel material for high-efficiency optoelectronic applications.However, it is still challenging to grow wafer-sized, highly uniform and strictly monolayer TMDCs continuous film through the conventional chemical vapor deposition (CVD) due to the uncontrollable growth kinetics. The evaporation rates and amounts of the heated precursors are uncontrollable because the saturation vapor pressure of the precursor is exponentially dependent on the temperature inside the furnace. The sulfurized film is thus consisted of a mixture of monolayer, bilayer and multiple layers of TMDCs. The film with such unreproducible quality is not applicable for real industrial applications.In this work, we provide a self-limiting growth strategy based on modified CVD process to prepare the wafer-sized monolayer TMDCs. Theoretical simulations were performed to understand the fundamental thermodynamically mechanism of the strictly monolayer growth. The property-variation in TMDCs due to difference in electronic structure between different layers of TMDCs can be significantly reduced based on this new approach. The following figure indicates that the PL spectra detected from different spots (spot 1 to 5) of the WS2 film. All spectra measured from the 4'' wafer-sized sample show characteristics unique to monolayer WS2. This poses a reliable route for the growth of large-area monolayer TMDCs, which is essential for their reliable and robust applications in nanoelectronic devices. Figure 1

Understanding and Controlling Band Alignment at the Metal/Germanium Interface for Future Electric Devices

Germanium (Ge) is a promising semiconductor as an alternative channel material to enhance performance in scaled silicon (Si) field-effect transistor (FET) devices. The gate stack of Ge FETs has been much improved based on extensive research thus far, demonstrating that the performance of Ge FETs is much superior to that of Si FETs in terms of the on-state current. However, to suppress the performance degradation due to parasitic contact resistance at the metal/Ge interface in advanced nodes, the reduction of the Schottky barrier height (SBH) at the metal/Ge interface is indispensable, yet the SBH at the common metal/Ge interface is difficult to control by the work function of metal due to strong Fermi level pinning (FLP) close to the valence band edge of Ge. However, the strong FLP could be alleviated by an ultrathin interface layer or a low free-electron-density metal, which makes it possible to lower the SBH for the conduction band edge of Ge to less than 0.3 eV. The FLP alleviation is reasonably understandable by weakening the intrinsic metal-induced gap states at the metal/Ge interface and might be a key solution for designing scaled Ge n-FETs.

Strain-Free Layered Semiconductors for 2D Transistors with On-State Current Density Exceeding 1.3 mA μm-1.

High-mobility and air-stable two-dimensional (2D) Bi2O2Se semiconductor holds promise as an alternative fast channel material for next-generation transistors. However, one of the key challenges remaining in 2D Bi2O2Se is to prepare high-quality crystals to fabricate the high-performance transistors with a high on-state current density. Here, we present the free-standing growth of strain-free 2D Bi2O2Se crystals. An ultrahigh Hall mobility of 160 000 cm2 V-1 s-1 is measured in strain-free Bi2O2Se crystals at 2 K, which enables the observation of Shubnikov-de Haas quantum oscillations and shows substantially higher (>4 times) mobility over previous in-plane 2D crystals. The fabricated 2D transistors feature an on-off current ratio of ∼106 and a record-high on-state current density of ∼1.33 mA μm-1, which is comparable to that of commercial Si and Ge n-type field-effect transistors (FETs) for similar channel length. Strain-free 2D Bi2O2Se provides a promising material platform for studying novel quantum phenomena and exploration of high-performance low-power electronics.

Scaled indium oxide transistors fabricated using atomic layer deposition

In order to continue to improve integrated circuit performance and functionality, scaled transistors with short channel lengths and low thickness are needed. But the further scaling of silicon-based devices and the development of alternative semiconductor channel materials that are compatible with current fabrication processes is challenging. Here we report atomic-layer-deposited indium oxide transistors with channel lengths down to 8 nm, channel thicknesses down to 0.5 nm and equivalent dielectric oxide thickness down to 0.84 nm. Due to the scaled device dimensions and low contact resistance, the devices exhibit high on-state currents of 3.1 A/mm at a drain voltage of 0.5 V and a transconductance of 1.5 S/mm at a drain voltage 1 V. Our devices are a promising alternative channel material for scaled transistors with back-end-of-line processing compatibility.

Investigation on the passivation, band alignment, gate charge, and mobility degradation of the Ge MOSFET with a GeO x /Al2O3 gate stack by ozone oxidation

Ge has been an alternative channel material for the performance enhancement of complementary metal–oxide–semiconductor (CMOS) technology applications because of its high carrier mobility and superior compatibility with Si CMOS technology. The gate structure plays a key role on the electrical property. In this paper, the property of Ge MOSFET with Al2O3/GeO x /Ge stack by ozone oxidation is reviewed. The GeO x passivation mechanism by ozone oxidation and band alignment of Al2O3/GeO x /Ge stack is described. In addition, the charge distribution in the gate stack and remote Coulomb scattering on carrier mobility is also presented. The surface passivation is mainly attributed to the high oxidation state of Ge. The energy band alignment is well explained by the gap state theory. The charge distribution is quantitatively characterized and it is found that the gate charges make a great degradation on carrier mobility. These investigations help to provide an impressive understanding and a possible instructive method to improve the performance of Ge devices.

Addressing source to drain tunneling in extremely scaled Si-transistors using negative capacitance

The impact of negative capacitance (NC) of the ferroelectric materials in controlling the direct source to drain tunneling (DSDT) in ultra-short channel FETs is presented in this paper. Besides, an analytical model is developed by solving 2-D Poisson’s equation incorporating the degeneracy of source/drain (S/D) regions. We demonstrate that in NC gate stack based Si channel FETs (NC-FETs), the scaling limit can be pushed down to 7 nm gate length, without using effective mass engineering and alternate channel materials. However, under severe subthreshold tunneling circumstances, we find that as the % content of tunneling current rises above the value of 50% in the net current, the subthreshold slope (SS) ceases to improve with the higher ferroelectric thickness. The rigorous analysis of DSDT-Negative drain induced barrier lowering (NDIBL) and impact of the S/D doping over DSDT is also incorporated in the paper. It is found that DSDT decreases drastically in the NCFET compared to baseline FETs due to the NC effect. Hence, using NC effect, transistor can be scaled down to 7 nm physical gate length with SS < 80 mV/dec and IOFF< 70 nA/μm compared to 173 mV/dec and 1.5×106 nA/μm, respectively for the baseline FET at the same gate length.

(Invited) Atomic-Scale Investigations on the Wet Etching of Group IV Semiconductors in Acidic H2O2 Solution: The Case Ge Versus Si-Ge

Over the decades, Si-based complementary metal–oxide semiconductor (CMOS) technology has challenged the semiconductor industry in improving device performance while maintaining the scaling requirements. However, the use of the group IV semiconductor as a channel material is reaching its ultimate limit due to physical complications, such as gate leakage, parasitic resistance/capacitance and size channel effects [1]. Some workaround solutions have implemented trigate structures, while novel gate-all-around (GAA) nanowire or nanosheet devices are also explored.[2] One of the core challenges for these devices is the highly selective removal of sacrificial SiGe epitaxial layers to release active parts of the device.[3] This aspect is further complicated by the introduction of Ge as an alternative channel material of higher mobility.[4]Wet-chemical processing remains an essential step for new nanodevice fabrication. With channel widths of only a few tens of atomic layers, etching control up to the atomic-layer-scale is necessary. To achieve such a level of precision, basic insights in semiconductor/electrolyte interactions are indispensable. Unlike for Si, the surface chemistry of Ge in wet-chemical solutions has remained relatively unexplored. One of the factors impeding in-depth surface analysis is the high reactivity of Ge in air. For this reason, the use of an integrated surface preparation apparatus in a surface analytical tool is crucial to rule out controversial effects of atmospheric oxygen and water.In this work we discuss the wet-chemical etching of Ge (100) in acidic H2O2 solutions. Kinetic studies were performed using inductively coupled plasma mass spectrometry (ICP-MS). Under reaction limited conditions, we showed that surface chloride chemistry has a profound impact on the dissolution kinetics and the anisotropy of wet etching, while proton effects were found to be less important. These results served as a starting point for the comparison of Ge versus SiGe. We provide an atomic scale investigation on the influence of the Si bulk concentration versus the kinetics of etching. The results are complimented by synchrotron X-ray photoemission spectroscopy (SXPS) measurements. We highlight the use of an integrated surface preparation chamber directly connected to SXPS apparatus to obtain fundamental insights into the surface chemistry of these technologically relevant group IV semiconductors. The results suggest that, while the release of Ge atoms from surface sites is favorable, the Si oxide chemistry determines the etching kinetics of SiGe. Basic etching schemes help to explain the formation of a (quasi) self-limiting oxide on SiGe. Energy dependent surface composition analysis provided insight into the nature of the oxide layer that showed depletion of Ge components at the outer surface due to pull out effects.[6]In summary, this research provides a new outlook for various applications such as biomedicine [7], photodetectors [8] and for light absorbing and harvesting of solar energy [9]. In addition, it serves as an eye-opener for the potential of semiconductor surface chemical studies using an UHV-integrated chemical cell connected to XPS to study etching systems.[1] R. Pillarisetty, Nature 479 (2011), p. 324-328.[2] J. Ryckaert et al., IEDM San Francisco, CA, USA, pp. 29.4.1-29.4.4 (2019)[3] K. Wostyn, F. Sebaai, J. Rip, H. Mertens, L. Witters, R. Loo, A. Y. Hikavyy, A. Milenin, N. Horiguchi, N. Collaert, A. Thean, P. Mertens, S. De Gendt and F. Holsteyns, ECS Trans., 69, 147 (2015).[4] M. Kobayashi, G. Thareja, M. Ishibashi, Y. Sun, P. Griffin, J. McVittie, P. Pianetta, K. Saraswat, Y. Nishi: J. Appl. Phys. 106, p. 104117-7 (2009).[5] G. H. A. Abrenica, M. V. Lebedev, G. Okorn, D. H. van Dorp and M. Fingerle, Appl. Phys. Lett., 113, 062104 (2018)[6] Graniel Harne A. Abrenica, Mikhail V. Lebedev, Mathias Fingerle, Sophia Arnauts, Nazaninsadat Bazzazian, Wolfram Calvet, Clement Porret, Hugo Bender, Thomas Mayer, Stefan de Gendt and Dennis H. van Dorp, J. Mater. Chem. C, 2020, 8, 10060 (2020)[7] H. Geng, J. Dai, J. Li, Z. Di and X. Liu, Sci. Rep. 6, 37474 (2016)[8] J. Michel, J. Liu and L. C. Kimerling, Nat. Photonics 4, 527534 (2010)[9] S. L. Shinde, T. D. Dao, S. Ishii, L-W. Nien, K. K. Nanda and T. Nagao, ACS Photonics 4, 1722-1729 (2017)

Mobility enhancement techniques for Ge and GeSn MOSFETs

The performance enhancement of conventional Si MOSFETs through device scaling is becoming increasingly difficult. The application of high mobility channel materials is one of the most promising solutions to overcome the bottleneck. The Ge and GeSn channels attract a lot of interest as the alternative channel materials, not only because of the high carrier mobility but also the superior compatibility with typical Si CMOS technology. In this paper, the recent progress of high mobility Ge and GeSn MOSFETs has been investigated, providing feasible approaches to improve the performance of Ge and GeSn devices for future CMOS technologies.

Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

(Invited) Stress Simulations of Fins, Wires, and Nanosheets

As the scalability of FinFET architectures is stretched to its limits in the most advanced technologies, industry and research are looking to the next candidates to scale the gate lengths a few nanometers closer to 10nm. Nanosheets and nanowires are such candidates, and specifically the introduction of the former is considered by a major industry player [1]. The inflection point of the transition from fins to sheets and wires depends on multiple trade-offs, of which channel stress is one: stress in the new architectures should preferably match the one in fins to become a viable contender to FinFET technologies. The introduction of stress in fins, wires and sheets, including devices with alternative channel materials, has been studied by several excellent publications from others [2-5], as well as by us [6-8].This work will focus on TCAD simulations of channel stress in fins, wires and sheets with typical 5nm-node dimensions. We focus on stress generation resulting from the following interacting stressors: 1. Lattice mismatch stress resulting from a different Ge composition between the substrate and the channel 2. lattice mismatch stress between the source/drain regions and the substrate (and channel) 3. for the case of wires and sheets, lattice mismatch stress from the sacrificial layers that are grown in between the wires and sheets, and that are removed in the replacement gate module. All simulations are performed with Sentaurus Process [9].For Si0.5Ge0.5 nanowires on a Si0.75Ge0.25 virtual substrate (Fig. 1) with Si0.5Ge0.5 epitaxially grown source/drains, the longitudinal channel stress at the end of processing in the top, middle and bottom wires is plotted in Fig. 2, and compared to the stress in corresponding fin structures. The following observations can be made: 1. Compressive (i.e. negative) channel stress is found, making this configuration suitable for p-type devices. 2. stresses are strongly dependent on the original fin or wire length, as stress relaxation occurs during fin/ wire cut. 3. there is significant difference between the stress in the top, middle and bottom wire, especially for short wire lengths. 4. (absolute) stresses in wires are higher than in fins, thanks to the presence of the sacrificial layers that limit stress relaxation in wires during wire cut [6].Scaling the devices from 8nm-node to 3nm-node dimensions decreases the absolute stress in fins and wires, Fig. 3. However, significant stress values are predicted down to the smallest nodes, especially for nanowires (> 1GPa). For all nodes, the stress in wires outperforms the one in fins by 50-70%.Fig. 4 shows the channel stress in nanowires and sheets versus device width. Moving from wires (i.e. a device width of 7nm) to larger widths, corresponding to sheets, tends to decrease the volume ratio of the source/drain stressor to the channel. As a consequence, lower absolute stresses are predicted for wider sheets, even when the wire/sheet pitch is scaled along with the device width. In general the highest stresses are found when the channels are thin, provided the mechanical stability of the channel is not compromised, which is something that has not been assessed in this work.Finally, the goal of this work is to study one particular concern for source/drain epitaxy in nanowires and nanosheets: in the presence of internal spacers, the source/drain epi starts from the nanowires as well as from the substrate, and may not join perfectly, leading to stress loss (Fig. 5). This work will perform a worst-case estimate of the stress loss in the presence of various defective interfaces. The TCAD results will be compared with experimentally measured strain using nano-beam diffraction [7-8].

(Invited) Ferroelectric-HfO2 Devices: Physics and Applications

1. Introduction Ferroelectric-HfO2 (FE-HfO2) is a key technology enabler for energy-efficient memory devices because of its high scalability and CMOS-compatibility [1]. FE memory device is low-power, high-speed and high reliability by field-driven operation. FE memory device can be implemented in the form of capacitor, resistor, and transistor, which provides us design flexibility of memory system. Thanks to the material break-through and the device architecture innovation, FE memory device opens up new opportunities in memory market. In this talk, I will overview our recent research progress on FE-HfO2 memory devices and discuss future perspectives. 2. Capacitor memory - NVSRAM The most mature device structure is capacitor type. It is natural to replace conventional FE-material by scalable FE-HfO2. We can take an advantage of low power operation of FE-HfO2 for smart power management in IoT application. IoT sensor node devices are expected to operate in an intermittent mode. The active rate of a transistor is much lower than clock frequency in IoT device. In order to suppress standby leakage power, especially in SRAM, it is important to bring the transistors in sleep mode as much as possible. Normally-off computing is the idea that stores the current state data in NV memory, turns the power off, and restore the data after power-on without much latency and power overhead. NV-SRAM [2] has been revisited by using FE-HfO2 which realizes good scalability as well as cost effective process. NV-SRAM has been designed, fabricated by integrating FE-HfO2 capacitor [3] in back-end process as shown in Fig. 1. Store, power-off, and recall operation are successfully demonstrated. 3. Resistive memory - FTJ Ferroelectric Tunnel Junction (FTJ) memory is an emerging memory for high capacity memory. A ferroelectric thin film is sandwiched by two electrodes, which works as resistive change memory, as shown in Fig. 2. FTJ was proposed back in 1970s [4] and current state-of-the-art nanoscale ferroelectric thin film technologies are to finally realize it. FTJ utilizes polarization switching to change on-sate and off-state tunneling electroresistance (TER). Design guideline and high TER as much as >30 has been recently demonstrated by FE-HfO2 (Fig. 2) [5]. FTJ also shows multi-level cell operation and high resistance, which are useful for hardware AI application. Moreover, scalability has been thoroughly investigated by self-consistent potential and non-equilibrium Green function method to compete with other high capacity memories (Fig. 3) [6]. 4. Transistor memory - FeFET Ferroelectric FET (FeFET) memory is a transistor which has a thin FE layer as gate insulator. This is another type of device structure for high capacity memory. Recently, 3D stacked FeFET has been proposed [7], which can possibly compete with NAND flash memory in terms of memory capacity.There are several challenges to realize such 3D stacked FeFET using conventional poly-Si channel. Poly-Si channel has low mobility and forms a low-k interfacial layer which causes voltage loss and reliability degradation by charge trapping. In this work, we propose to use amorphous oxide semiconductor, IGZO [8], as an alternative channel material. IGZO channel provides high mobility as a deposited channel and prevent low-k interfacial layer formation. We have demonstrated ferro- electricity in the combination of FE-HfO2 and IGZO (Fig. 4), and large memory window with nearly ideal subthreshold swing and high endurance operations [9]. 5. Conclusions FE-HfO2 is a key technology enabler for energy-efficient computing because of its high scalability and CMOS-compatibility. NVSRAM serves for smart power management in IoT applications. FTJ and FeFET have a potential for low power and high capacity memory as well as machine learning accelerator. Acknowledgment The author acknowledges Nozomu Ueyama, Yusaku Tagawa, Fei Mo, Kiyoshi Takeuchi, Takuya Saraya and Toshiro Hiramoto for technical discussion and help. This work is partly supported by JST CREST 16815651, JST PRESTO 15656058, MEXT KAKENHI 16K18085 and 18H01489.

(Invited) Epitaxial Growth of Ge/III-V Films and Hetero-Layer Lift-off for Ultra-Thin GeOI Fabrication

Ge have been considered as an alternative channel material to Si as well as a promising base material for optical components, adding new functions into current Si-LSI. It is necessary to form high quality Ge layers onto Si substrate for realization of Si/Ge monolithic 3D (M3D) devices. Combing high quality hetero-epitaxial growth of Ge/III-V semiconductors, low-temperature bonding, and an advanced lift-off technique, we have achieved Ge layer transfer on Si substrate, possessing excellent Ge crystallinity and electrical properties. The advanced HEtero-Layer-Lift-Off (HELLO) technique utilizing SiGe-based hetero-epitaxy and dozens digital etching (DDE) processes are demonstrated to realize high quality and ultra-thin Ge-on-insulator (GeOI) structures for ultimately scaled CMOS devices on Si platform.

Performance Measures of Different Gate Oxide Materials in Gate All Around Fet

The classical planar Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is fabricated by oxidation of a semiconductor namely Silicon. In this generation, an advanced technique called 3D system architecture FETs, are introduced for high performance and low power quality of devices. Based on the limitations of Short Channel Effect (SCE), Silicon (Si) FET cannot be scaled under 10nm. Hence various performing measures like methods, principles, and geometrics are done to upscale the semiconductor. CMOS using alternate channel materials like GE and III-Vs on substrates is a highly anticipated technique for developing nanowire structures. By considering these issues, in this paper, we developed a simulation model that provides accurate results basing on Gate layout and multi-gate NW FET’s so that the scaling can be increased few nanometers long and performance limits gradually increases. The model developed is SILVACO that tests the action of FET with different gate oxide materials.