All-pass Circuits Research Articles

Equivalence of Two Active RC All-Pass Circuits

The equivalence of two active RC all-pass circuits, proposed by different authors, but in the same journal, with a gap of three years, is established. It is shown that the earlier circuit had a flexibility which is absent in the later publication.

Метод синтеза согласованного фильтра

The paper studies the method of approximating the complex transfer coefficient of a matched, physically realizable, stable filter having the minimum required number of functional units. We propose a method of approximation of the complex transfer coefficient of a matched filter, namely: approximation by the complex coefficient of the device obtained by cascade connection of a linear time-invariant system and an allpass circuit. The linear time-invariant system has an amplitude-frequency response equal to the modulus of the spectral density of the signal with which the filter is matched. The complex transfer coefficient of the all-pass circuit is defined with taking into account the required phase-frequency response of the matched filter. As a result, the number of matched filter elements is significantly reduced.

Synthesis of Reflection-Type Coupled Line All-Pass Circuit With Arbitrary Prescribed Wideband Flat Group Delay

In this letter, the analytical design method of a reflection-type coupled line all-pass circuit with arbitrary predefined wideband flat group delay (GD) is presented. The proposed circuit consists of 90° hybrid and coupled lines with a short-circuited load. The proposed structure is simple and does not require any iterative process to obtain optimum circuit parameters. Theoretical and experimental results are provided for validation of the proposed structure. The prototype circuits were fabricated at a center frequency of 2.5 GHz with 2 and 4 ns flat GD responses. The measurement results agreed well with the simulation and theoretical predicted results.

Frequency Limitations of First-Order $g_{m} - RC$ All-Pass Delay Circuits

All-pass filter circuits can implement a time delay but, in practice, show delay and gain variations versus frequency, limiting their useful frequency range. This brief derives analytical equations to estimate this frequency range, given a certain maximum allowable budget for variation in delay and gain. We analyze and compare two well-known gm - RC first-order all-pass circuits, which can be compactly realized in CMOS technology and relate their delay variation to the main pole frequency. Modeling parasitic poles and putting a constraint on gain variation, equations for the maximum achievable pole frequency and delay variation versus frequency are derived. These equations are compared with simulation and used to design and compare delay cells satisfying given design goals.

NEW ALL-PASS FILTER CIRCUIT COMPENSATING FOR C-CDBA NON-IDEALITIES

In this paper, a CMOS current controlled current differencing buffered amplifier (C-CDBA) realization is presented. Also, a new first-order all-pass filter that compensates for some C-CDBA non-idealities is given as an application example. The all-pass filter circuit has low output impedance for easy cascadability and it can be made electronically tunable using the proposed C-CDBA implementation. The theoretical results are verified with SPICE simulations.

Electronically tunable first-order all-pass circuit employing DVCC and OTA

This article presents a realisation of an electronically tunable first-order all-pass circuit employing a differential voltage current conveyor (DVCC), an operational trans-conductance amplifier (OTA) and two MOS conductance. The circuit can realise two all-pass characteristics by choosing the current output of the OTA. Additionally, the circuit parameters ω0 and H can be set independently by tuning the circuit active components electronically. Sensitivity analysis shows that the circuit enjoys very low sensitivity to the circuit components. An example is given together with simulated results by PSPICE.

Classical circuit theory

This book begins with the basic principles of circuits, derives their analytic properties in both the time and frequency domains, and states and proves the two important theorems. It then develops an algorithmic method to design common and uncommon types of circuits, such as prototype filters, lumped delay lines, constant phase difference circuits, and delay equalizers. The material also discusses the relation between gain and phase, linear and minimum phase functions, group delay, sensitivity functions, scattering matrix, synthesis of transfer functions, approximation of filter functions, all-pass circuits, and circuit design by optimization. This book fills a need for a modern text on the mathematical foundations of passive circuits in general and passive filter design in particular. The mathematical foundations are what classical circuit theory, which is the subject of this book, is all about. It is old, but it has survived the test of time and it is still relevant today because it is basic.

High input impedance VM-APSs with grounded passive elements

Three new circuit topologies for first-order all-pass filters, each with two variations, realising six new first-order voltage-mode all-pass sections are proposed. Each circuit employs two differential voltage current conveyors and three grounded passive components, ideal for IC implementation. All the circuits possess high input impedance, which is a desirable feature for voltage-mode circuits. As an application, a new quadrature oscillator circuit is realised using one of the proposed all-pass circuits. PSPICE simulations using 0.5 mum CMOS parameters confirm the validity and practical utility of the proposed circuits

Allpass based on a generalized divider principle

This paper deals with a new allpass structure based on a generalized divider principle. An efficient modification of the basic general divider structure using Antoniou's GICs is presented and the corresponding 1st- and 2nd-order allpass circuits are derived. A detail discussion is devoted to the optimized design of the 2nd-order allpass, taking minimization of the active elements nonidealities and dynamics optimization into account. An original design procedure is described and documented on numerical examples.

Switched-current wave group delay equalisers

To improve the elliptic filter step response, group delay equalisers are often cascaded with the filters. The paper describes the design of switched-current (SI) group delay equalisers using the wave synthesis technique. This design is based on a new all-pass circuit, where the poles are generated using wave structures. Simulation results are included demonstrating that the 3rd-order SI group delay equaliser can reduce the amount of overshoot in the 100kHz elliptic low-pass filter step response by ≥50%. This is as a result of reducing the filter group delay variation from 2.29 μs to 0.32 μs when the group delay equaliser is employeds.

Parasitic‐insensitive switched‐capacitor variable all‐pass filters that have small total capacitance

This paper proposes a method of constructing first- and second-order switched-capacitor variable all-pass circuits that have small total capacitance and are parasitic-insensitive. A first-order circuit, in which the peak group delay at zero angular frequency can be specified by using a programmable capacitor array, and a second-order circuit that has a first-order subcircuit, in which the peak bandpass group delay and the corresponding angular frequency (peak angular frequency) can be specified independently, have already been presented. Those constructions, however, have the problem that the capacitance spread is generally enlarged in the first-order circuit (defined here as the maximum capacitance when the minimum capacitance is normalized to 1). This increases the total capacitance in both the first- and second-order circuits and makes the second-order circuit parasitic-sensitive. This paper, on the other hand, proposed circuits that are parasitic-insensitive and have smaller total capacitances than the circuits proposed in the past. The second-order circuit proposed in the past also has the problem that the peak angular frequency cannot be set higher than half the Nyquist angular frequency, but this is possible in the proposed second-order circuit. Another point is that the number of operational amplifiers is reduced by one in the proposed circuit. The calculated amplitude element-sensitivities of the first- and second-order circuits are smaller than the past values. The proposed circuit was experimentally constructed using discrete components, and a satisfactory result was obtained. © 1999 Scripta Technica, Electron Comm Jpn Pt 3, 82(10): 50–62, 1999

Generation of current conveyor-based all-pass filters from op amp-based circuits

It is shown that two of the recently reported voltage mode and current mode current conveyor-based all-pass circuits can be generated from the well known single input op amp all-pass configuration. It is also found that two other voltage mode current conveyor-based all-pass circuits are related directly to the differential input op amp all-pass structure. Several new grounded capacitor all-pass circuits are introduced. A new universal biquad circuit which realizes complex poles and employs a single current conveyor is also given. PSpice simulation results are included.

A high-frequency integrable bandpass filter configuration

Inductorless bandpass filters have in the past been realized using all-pass circuits based on op amps. This work replaces the op amps with integrable fixed gain amplifiers to create the bandpass filter. Values of Q exceeding 100 with resonant frequencies approaching 50 MHz can be achieved with an integrated circuit implementation. A method to reduce the sensitivity of Q with respect to temperature is reported.

Filter cirucit realization with single operational amplifier and LCR elements and its application for allpass response

AbstractThis paper discusses a method for configuration of a single operational amplifier filter circuit using one operational amplifier (Op Amp) and LCR elements. the proposed single Op Amp filter cirucit has a constant resistance input impedance and a zero output impedance. It allows realization of any stable transfer function.In this paper, a method for realizatio of an allpass function in investigated in particular and its design method is presented. Actually, a computer simulation and an experiment with a test circuit made of discrete components are carried out for a cirucit to realize a fifth‐order allpass function. the cirucit performance is compared with that of a cascaded scheme of Deliyannis circuits. the element sensitivity in regard to the LCR elements, the frequncy characteristics of the Op Amp and the sensitivity of the inductor L with respect to Q are derived. It is shown that the proposed allpass circuit has low element sensitivity and the number of necessary reactance elements is identical to the order of the transfer function.

High Input Impedance All-Pass Circuit

A novel operational transconductance amplifier (OTA) based all-pass (AP) circuit exhibiting essentially infinite input impedance and facilitating non-interactive electronic control of gain and phase without disturbing the AP condition is proposed. A large amount of gain is attainable from the circuit as the scale factor is a function of the product of transfer gain (gm) of OTA and grounded resistor which can be made voltage variable. The circuit can also be made digitally programmable by controlling the bias currents of OTAs with DAC.

A single-chip image rejecting receiver for the 2.44 GHz band using commercial GaAs-MESFET-technology

A single-chip receiver for the 2.44 GHz band has been designed. To minimize the number of chip connections as well as external components, an image rejecting architecture has been chosen. A two-stage voltage controlled ring oscillator is used as a quadrature LO-source. The IF phase relationship is achieved with RC allpass circuits. Special attention is paid to keep the design insensitive to process variations. The 3-mm/sup 2/ chip has been fabricated with commercial 1-/spl mu/m E/D GaAs MESFET technology and comprises an RF preamplifier, a voltage controlled ring oscillator, a phasing type image reject mixer, an IF preamplifier and a prescaler (division by 16). Except for the power supply and the frequency tuning voltage, no external components are required for basic operation. Prototype devices from two wafer runs were investigated. Power consumption from a single supply voltage of 5 V is 0.6 W. An image rejection of 34 dB is measured over a 130 to 280 MHz IF bandwidth. With a simple input symmetrizing and matching network, a conversion gain of 34 dB and a noise figure of 6.5 dB are achieved. The short term frequency instability of the free running ring oscillator is 400 kHz. With simple passive analog phase lock circuitry, an SSB phase noise of -74 dBc/Hz at 100 kHz offset is attained. >

Improved design of digital filters satisfying a combined loss and delay specification

The classical solution to the design of both analogue and digital filters with magnitude and delay constraints is to cascade a minimum phase circuit satisfying the magnitude constraint and an allpass circuit that equalises the delay distortion caused by the first. Such a solution is inefficient and, in this paper, a simple method is considered whose aim is to meet both constraints simultaneously in the digital case. The filter model that is used is a parallel arrangement of allpass circuits which allows a large range of transfer functions to be realised. This model is efficient in the sense that the number of multipliers required equals to the filter order. A sequential quadratic programming technique coupled with a single-line template is used to find the set of coefficients which minimises the squared error. A novel way of setting up the frequency grid is proposed which aims to increase the loss quickly in the transition band. The choice of suitable starting points has an important impact on the length of the optimisation process. A particularly efficacious choice is presented here. Examples are provided illustrating the method, including lowpass, bandpass and multiple bandpass designs, as well as comparing it with a recently reported technique.

Chebyshev phase of IIR networks for pulse expanding

The paper describes a method for designing IIR allpass circuits for pulse expanding, the phase of which approximate to a squared phase in the Chebyshev sense in the given frequency region. The method is based on the solution of a linear equation system which provides a final solution with a very small number of iterative cycles.

A method of designing parallel‐type pseudo‐minimum‐phase FIR QMF banks

AbstractSubband coding (SBC) is a low bit‐rate speed transmission system in which a quadrature mirror filter (QMF) is used to split a speech into frequency bands of the transmitter and recombine these subband signals to form an approximation to the input speech at the receiver. In the conventional parallel‐type FIR multiband pseudo‐QMF bank, the linear‐phase filters are employed in the transmitter and receiver, which gives rise to a problem wherein a large delay is produced.This paper presents a design method for the equal‐bandwidth parallel‐type QMF bank with smaller delay by allowing some delay distortion. The amplitude and phase constraints on each channel filter are shown so that the transmitted signal can be reconstructed approximately at the receiver. A design example is presented for the 4‐band filter bank, where the amplitude constraint is satisfied by a minimum‐phase filter and the phase constraint is satisfied by a allpass circuit cascaded to the filter. The designed low‐pass filter is of 50 percent roll‐off, and the bandpass filter is a 100 percent roll‐off. The attenuation is 43 dB. The delay is almost flat in characteristic and the amount is reduced to approximately one‐half that of the linear‐phase filter bank.

Electronically tunable OTA-based all-pass circuit

A simple operational transconductance amplifier (OTA)-based circuit implementing first-order all-pass function is presented. Besides using a single OTA, the circuit employs a grounded capacitor and as many as four resistors. The gain of the circuit is electronically-tunable through transconductance gain of OTA and a grounded resistor, which can be be made voltage dependent. The circuit provides non-interactive tuning of phase and gain without disturbing the realizability condition. The circuit is capable of providing a substantial amount of gain, as the scale factor is a function of two gain-controlling parameters. The circuit is highly stable against temperature variations, since the realizability condition is a function of the resistor ratio.