Abstract

A single-chip receiver for the 2.44 GHz band has been designed. To minimize the number of chip connections as well as external components, an image rejecting architecture has been chosen. A two-stage voltage controlled ring oscillator is used as a quadrature LO-source. The IF phase relationship is achieved with RC allpass circuits. Special attention is paid to keep the design insensitive to process variations. The 3-mm/sup 2/ chip has been fabricated with commercial 1-/spl mu/m E/D GaAs MESFET technology and comprises an RF preamplifier, a voltage controlled ring oscillator, a phasing type image reject mixer, an IF preamplifier and a prescaler (division by 16). Except for the power supply and the frequency tuning voltage, no external components are required for basic operation. Prototype devices from two wafer runs were investigated. Power consumption from a single supply voltage of 5 V is 0.6 W. An image rejection of 34 dB is measured over a 130 to 280 MHz IF bandwidth. With a simple input symmetrizing and matching network, a conversion gain of 34 dB and a noise figure of 6.5 dB are achieved. The short term frequency instability of the free running ring oscillator is 400 kHz. With simple passive analog phase lock circuitry, an SSB phase noise of -74 dBc/Hz at 100 kHz offset is attained. >

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