All-pass Networks Research Articles

A Compact and Wideband mmWave Passive CMOS Circulator Based on Switched All-Pass Networks

A Compact and Wideband mmWave Passive CMOS Circulator Based on Switched All-Pass Networks

Low-Noise Low-Power Ultrasound AFE With Continuous TGC Built in Both TIA and Beamformer.

This article presents a low-noise high-power-efficiency analog front-end (AFE) for capacitive-micromachined-ultrasonic transducers (CMUT). Implemented in 28-nm CMOS technology, the proposed AFE features three-stage continuous time-gain compensation (TGC) embedded in both trans-impedance amplifiers (TIAs) and an analog beamformer to provide a large compensation range with no extra power-consumption cost. The use of noise cancellation and capacitive feedback optimizes the noise performance of TIAs. The first stage of the TGC is built in the TIA by adjusting the positive and negative resistance loads, which are composed of voltage-controlled transistor arrays. An all-pass passive network is used as the delay unit of the analog beamformer, meanwhile achieving the second TGC stage. Phase shift for all frequency components in the ultrasound pass-band is manifested as a delay to the echoes. The third stage of the TGC is merged with a summing unit, which is a closed-loop amplifier with variable resistance feedback. The design takes into account the ability to handle large signals and power consumption, with TIA and beamforming operating at voltages of 2.5 V and 0.9 V, respectively. Experimental results show that the proposed AFE achieves a 2.11 pA/√Hz input-referred noise (IRN) at the 5 MHz center frequency of the echoes while consuming only 1.02 mW/channel. A total exponential TGC range of 60 dB with continuous ranges of 12 dB, 24 dB, and 24 dB assigned to three stages has been verified for this work.

A novel PMOS transistors based first-order all-pass network

In this paper, a new voltage-mode first-order all-pass network is introduced. It is realized by using only four p-channel metal–oxide–semiconductor transistors, one resistor and one capacitor. The proposed filter enjoys the feature of high input impedance and does not require any additional current source. It is also free from any kind of passive element matching constraint. In order to test the workability of the proposed structure, a second-order all-pass network and quadrature oscillator are presented. Personal simulation program with integrated circuit emphasis using 0.18 µm, level-7 complementary metal-oxide-semiconductor process parameters with ± 0.9 V supply voltages are used to validate the performance of the proposed structure.

A 2.2–4.2-GHz Wideband Analog Phase Shifter MMIC With Low RMS Phase/Amplitude Error

This letter presents a 2.2–4.2-GHz 360° continuous-tuned phase shifter (PS) using the Gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) technology. A new method for broadband analog PS design based on a tunable low-pass network (LPN), a tunable high-pass network (HPN), and a magnetically coupled all-pass network (MCAPN) configuration is proposed to achieve uniform phase shifting and flat amplitude response at the same time for each phase-shifting state. The fabricated PS demonstrates a low average insertion loss (IL) of 4.9 dBC a low root-mean-square (rms) phase error of less than 5.5°, and a low rms amplitude error of less than 0.47 dB between 2.2 and 4.2 GHz. The proposed analog PS has the most flattened phase performance compared with previously reported pass PSs over a wide bandwidth.

A Compact 26.5–29.5-GHz LNA-Phase-Shifter Combo With 360° Continuous Phase Tuning Based on All-Pass Networks for Millimeter-Wave 5G

This article presents a compact integrated receiver front-end for phased-arrays at 5G n257/n261 band (26.5-29.5 GHz) employing both a low-noise amplifier (LNA) and a novel passive phase-shifter based on variable-phase all-pass networks. The proposed phase-shifter topology is analysed and designed using 0.25 μm BiCMOS achieving continuous tuning capabilities with 360° phase range over a 25-33 GHz frequency range under 0.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of area. The proposed phase-shifter is measured standalone, achieving 8.3 ± 0.55 dB losses at 29 GHz with an RMS gain error below 0.6 dB across the entire frequency range. When quantizing the continuous phase-shift into 6 bits, an RMS phase error <; 3° is obtained. To build the LNA-Phase-shifter combo, the phase-shifter is then integrated with an LNA optimized for compactness, which was measured standalone, showing a noise figure below 3.2 dB across the n257/n261 band and 20 dB gain under 0.0625 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of area. The small size of both the phase-shifter and LNA enables an ultra-compact phased-array receiver front-end under 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of area. The front-end is measured, achieving 11.5 ± 0.53 dB of gain, RMS gain error below 0.42 dB and RMS phase error below 3.2° over the entire n257 band, measured input-referred P1dB of -25 dBm and a 15 mW DC power consumption.

A Low Insertion Loss Variation Trombone True Time Delay in GaAs pHEMT Monolithic Microwave Integrated Circuit

A wideband true time delay is proposed based on 0.25- μm GaAs pHEMT technology. The novel trombone topology is adopted for achieving low variation in insertion loss of different delay states. The fourth-order and second-order inductive all-pass networks (APNs) are operating as delay cells between input and output lines. By selecting different transmission ways, 3 bit with the step of 14 ps and maximum delay range of 98 ps are realized. Measurement results show the insertion loss of 3.8-10.5 dB over the frequency bandwidth of 6-16 GHz. The variation in insertion loss is less than ±1.4 dB. The chip area with pads is 1.955 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the power consumption is 110 mW.

Dual Output Voltage Differencing Buffered Amplifier Based Active -C Multiphase Sinusoidal Oscillator

A multiphase sinusoidal oscillator (MSO) using dual output voltage differencing buffered amplifier (DO-VDBA) is presented in this paper which provides n equally spaced phase sinusoids of equal magnitudes. The proposed MSO topology is realized using the first order all pass network (APN). In the proposed structure the output voltages are made available at low impedance nodes which makes the proposed MSO easy for cascadability. Making the proposed structure a resistorless structure is a major challenge. The main benefits of the structure are easy integration and less power losses. The formulation of frequency and condition of oscillation is derived mathematically. The oscillation frequency can be tuned electronically, is an added advantage of the proposed MSO. The effect of device non-idealities is also discussed in the study. To assess the proposed MSO performance further Monte Carlo analysis was carried out. The workability of the proposed structure is verified through SPICE simulations for a three (n=3) and four (n=4) phases MSO, and the obtained simulated results are in close agreement with the theoretical values. The total harmonic distortion (THD) is found to be quite low.

A multi-octave microwave 6-bit true time delay with low amplitude and delay variation in 65 nm CMOS

AbstractIn this paper, we describe the design, layout, and performance of a 6-bit TTD (true time delay) chip operating over the entire band of 2–18 GHz. The 1.15 mm2 chip is implemented using TSMC foundry 65 nm technology. The least significant bit is 1 ps. The design is based on the concept of all-pass network with some modifications intended to reduce the number of unit cells. Thus, the first three bits are implemented in a single delay cell. A peaking buffer amplifier between bit 4 and bit 5 is used for impedance matching and partial compensation of the insertion loss slope. The rms delay error of the TTD is &lt;1 ps over most of the frequency band and insertion loss is between 2.5 and 6.3 dB for all 64 states.

A Compact 3–30-GHz 68.5-ps CMOS True-Time Delay for Wideband Phased Array Systems

This article presents a compact 4-bit switched-line true-time delay (TTD) circuit over a wide frequency range extending from 3 to 30 GHz using novel delay elements. The delay elements, namely, the cascading coupled all-pass network (CAPN) and noncoupled all-pass network (NCAPN), were employed in the proposed TTD circuit to improve the delay-bandwidth product (DBW) while maintaining its compact size and low delay variation (DV). For comparison, a theoretical analysis for understanding the group delay feature of the APN with various coupling coefficients is presented along with low-pass network (LPN). To verify the proposed structure, the proposed delays are applied to construct the 4-bit switched-line TTD by utilizing two single-pole double-through (SPDT) and three double-pole double-through (DPDT) switches in a 28-nm CMOS process. The circuit has a compact size of 1.7 mm ×0.2 mm, with a maximum delay of 68.5 ps and a minimum delay of 4.6 ps. The measured average insertion loss is 13.5 dB, and the in/out return loss is better than 10 dB across 3-30 GHz. The measured rms delay and gain errors are less than 2 ps and 3.2 dB, respectively, over the operating frequency range. To the best of our knowledge, the proposed TTD achieves the largest figure of merit (FoM) among the integrated TTD circuits.

Variable-Phase All-Pass Network Synthesis and Its Application to a 14–54 GHz Multiband Continuous-Tune Phase Shifter in Silicon

This article presents a novel synthesis procedure to implement variable-phase all-pass networks (VP-APNs). The synthesis procedure is based on linear-phase all-pass transfer functions, enabling implementation at millimeter waves. Using the proposed synthesis, VP-APNs with analog and digital control are implemented for the first time in silicon. Using 0.25-μm BiCMOS, the VP-APNs are manufactured and measured, validating the synthesis procedure. Finally, the validated VP-APNs are combined to realize a phase shifter. By combining the analog and digitally controlled networks, we obtain a continuous-tune phase shifter with multiband capabilities, successfully covering several bands from 14 to 54 GHz. This includes Ku-, K-, Ka-, and V-band, as well as both 5G bands around 28 and 39 GHz.

All-Pass Network and Transformer Based SiGe BiCMOS Phase Shifter for Multi-Band Arrays

In this brief, an all-pass network (APN) based SiGe BiCMOS phase shifter (PS) is presented showing a root-mean-square (RMS) phase error lower than 5.6° for a 123 % of fractional bandwidth (BW) in a compact area. The APN s, which are designed for equally separated resonance frequencies from the center, are preferred to improve the phase flatness. This results in a low RMS error for a broadened BW . A transformer is utilized to succeed 180° phase shift, while the 90° of phase state is obtained by a higher-order APN . The bits are cascaded by multiple switches, which are designed for the minimal capacitive parasitic. The custom lumped components are utilized to realize the wideband filters. The presented bidirectional PS guarantee 4-bit of operation for about (5-to-30 GHz) 25 GHz of BW with a maximum 1.2 dB of RMS amplitude error in a 0.45 mm2 area, excluding pads. The presented SiGe BiCMOS passive PS achieved the lowest RMS phase error in a compact area with the widest BW , among its counterparts in the literature.

Large Group Delay in Microstrip Circuit Using Coupled Open Stubs and Collocated Ground Slots

This letter proposes a large group delay microstrip circuit using a quarter wavelength symmetric coupled open stub (SCOS) and collocated double slot at 2.4 GHz. A design approach based on matching the quality factor ( $Q$ ) of SCOSs and slot loaded line is proposed to arrive at the physical parameters of these resonators. It has been shown that coupled lines with collocated double ground slots have significantly higher group delay compared to the geometry with single open stub and slot in the ground. Electromagnetic susceptibility (EMS) of circuit has been analyzed using simulations. A design with peak group delay (PGD) value of more than 4.3 ns is fabricated and characterized to validate the design approach. In addition to the large PGD the realized circuit possesses wideband impedance matching characteristics similar to an all-pass network.

High Precision CMOS Integrated Delay Chain for X-Ku Band Applications

A high-precision delay chain circuit integrated in a 0.18- $\mu \text{m}$ CMOS technology working in the frequency bandwidth of 8–18 GHz has been designed and tested. The designed delay control integrated circuit with 5-bit delay control provides a maximum delay of 125 ps and has a delay resolution of 3.9 ps. Measured delay error of the fabricated chip is less than 9.3%, making it a considerably accurate delay control circuit. Low delay-error performance has resulted from incorporating a novel delay cell in this delay chain circuit. This newly proposed delay cell is a lumped-element coupled transmission line loaded with a second-order all-pass network (APN). The APN-loaded coupled line delay cell has larger delay-bandwidth product and is less prone to parasitic capacitances of inductor elements compared with conventional passive second-order APN delay cells. The fabricated chip utilizing the novel delay cell occupies an area of $0.9\times3.6$ mm2 and consumes 115.5- and 13.5-mW dc power from a 3.3-V voltage supply in its high- and low-power modes, respectively.

A Compact Ka-Band 4-bit Phase Shifter With Low Group Delay Deviation

This letter presents a compact $Ka$ -band 4-bit switch-type phase shifter with low group delay deviation (GDD) using 28-nm CMOS technology. A magnetically coupled all-pass network (APN) configuration is employed to achieve both equal and flat group delay characteristics versus frequency at each phase state. The measured rms phase error is 1.2°, and the gain error is 1.1 dB at 33 GHz. The average measured insertion loss is 12.8 dB at 33 GHz, and the input and output return losses are both lower than −10 dB from 29 to 37 GHz. The fabricated phase shifter has a compact size of 0.08 mm2 excluding pads, low GDD of ±4 ps, and rms group delay error of $Ka$ -band phase shifter has the lowest GDD per bandwidth (GDD/BW) compared with other reported passive phase shifters.

Novel Trombone Topology for Wideband True-Time-Delay Implementation

A novel trombone topology has been introduced for achieving controllable true time delay. The prominent aspect of the proposed topology is the ability to provide discrete variable delay with minimum insertion loss variation with delay settings. Furthermore, the effects of source impedance, output load, and line-terminating loads’ impedance mismatch on group delay variation are theoretically investigated for the proposed trombone topology. Moreover, based on this new topology, a prototype trombone delay circuit has been designed and fabricated in 0.18- $\mu \text{m}$ CMOS technology, operating over the frequency bandwidth of 8–18 GHz. This 3-bit delay integrated circuit provides a maximum delay of 109.3 ps with 15.6-ps delay step and utilizes conventional passive second-order all-pass network (APN) and novel passive fourth-order APN delay cells. Measurement results indicate an average insertion loss of 18.2–22.5 dB over the intended frequency band with a relatively low loss variation of less than ±1 dB for all delay settings. Measured group delay rms error is less than 4 ps. The core of the fabricated circuit occupies an area of $0.9\times2.1$ mm2 and draws 13.4 mA from a 3.3-V supply.

CMOS integrated delay chain for X-Ku band applications

A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 $$\upmu \hbox {m}$$ CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from 8 to 18 GHz. The fabricated chip occupies an area of $$1.2\times 2.7$$ mm$$^{2}$$ and has no DC power consumption.

A 14–50-GHz Phase Shifter With All-Pass Networks for 5G Mobile Applications

In this article, an ultra-broadband phase shifter (PS) with a 14–50-GHz bandwidth (defined by a phase error below 1/2 LSB) is presented to address the multiband requirements of 5G millimeter-wave (mm-wave) systems. The PS construction is based on all-pass networks (APNs), which have shown broad bandwidth capabilities in a lower frequency range. Aiming toward 5G mobile applications, the proposed 2-bit, 45° phase resolution PS was implemented in 0.25- $\mu \text{m}$ BiCMOS, manufactured, and measured, achieving an insertion loss of 7.4 ± 0.26 dB at 28 GHz and 10 ± 0.22 dB at 39 GHz, with an rms gain and phase error <0.27 dB and <4° from 24 to 30 GHz, respectively, and <0.33 dB and <6° from 37 to 43.5 GHz, demonstrating its capabilities to cover the 5G mm-wave spectrum.

On mitigating acoustic feedback in hearing aids with frequency warping by all-pass networks

Acoustic feedback due to the acoustic coupling between the microphones and loudspeakers at high gains can cause the hearing aid system to become unstable. This instability results in brief “howling” artifacts as magnitude and phase conditions fulfill the Nyquist stability criterion (NSC). We present a novel approach that uses all-pass networks to perform nonlinear spectral mapping that we call “freping,” a portmanteau for frequency warping. In this contribution, we focus on spectral manipulations on top of adaptive feedback cancellation (AFC) to break NSC for improved feedback reduction. A real-time, multichannel realization is presented, which has individual control of the warping degree in each frequency band. Freping helps mitigate the NSC and thus leads to improved feedback control, while distortions due to freping are fairly benign based on informal subjective assessments. Our current findings indicate that improvements in terms of the perceptual evaluation of speech quality (PESQ) and the hearing-aid speech quality index (HASQI) can be achieved with freping for a basic AFC (PESQ: 2.56 to 3.52 and HASQI: 0.65 to 0.78) at medium amplification; and an advanced AFC (PESQ: 2.75 to 3.17 and HASQI: 0.66 to 0.73) at high amplification. Additional results will be included in the final presentation.

20–50 GHz differential all‐pass networks for phase‐shifting applications

In this Letter, four differential All-Pass Networks are presented to introduce phase-shift at millimetre waves using a linear-phase synthesis procedure. The proposed networks achieve 1-3.5 dB insertion loss while having S 11 < − 10 dB across the whole bandwidth, showing an almost constant group-delay, an RMS gain error of less than 0.15 dB and a phase-error of less than ± 3.5 ° .

On Mitigating Acoustic Feedback in Hearing Aids with Frequency Warping by All-Pass Networks.

Acoustic feedback control continues to be a challenging problem due to the emerging form factors in advanced hearing aids (HAs) and hearables. In this paper, we present a novel use of well-known all-pass filters in a network to perform frequency warping that we call "freping." Freping helps in breaking the Nyquist stability criterion and improves adaptive feedback cancellation (AFC). Based on informal subjective assessments, distortions due to freping are fairly benign. While common objective metrics like the perceptual evaluation of speech quality (PESQ) and the hearing-aid speech quality index (HASQI) may not adequately capture distortions due to freping and acoustic feedback artifacts from a perceptual perspective, they are still instructive in assessing the proposed method. We demonstrate quality improvements with freping for a basic AFC (PESQ: 2.56 to 3.52 and HASQI: 0.65 to 0.78) at a gain setting of 20; and an advanced AFC (PESQ: 2.75 to 3.17 and HASQI: 0.66 to 0.73) for a gain of 30. From our investigations, freping provides larger improvement for basic AFC, but still improves overall system performance for many AFC approaches.