Novel Trombone Topology for Wideband True-Time-Delay Implementation

Abstract

A novel trombone topology has been introduced for achieving controllable true time delay. The prominent aspect of the proposed topology is the ability to provide discrete variable delay with minimum insertion loss variation with delay settings. Furthermore, the effects of source impedance, output load, and line-terminating loads’ impedance mismatch on group delay variation are theoretically investigated for the proposed trombone topology. Moreover, based on this new topology, a prototype trombone delay circuit has been designed and fabricated in 0.18- $\mu \text{m}$ CMOS technology, operating over the frequency bandwidth of 8–18 GHz. This 3-bit delay integrated circuit provides a maximum delay of 109.3 ps with 15.6-ps delay step and utilizes conventional passive second-order all-pass network (APN) and novel passive fourth-order APN delay cells. Measurement results indicate an average insertion loss of 18.2–22.5 dB over the intended frequency band with a relatively low loss variation of less than ±1 dB for all delay settings. Measured group delay rms error is less than 4 ps. The core of the fabricated circuit occupies an area of $0.9\times2.1$ mm2 and draws 13.4 mA from a 3.3-V supply.