ALICE Inner Tracking System Upgrade Research Articles

ALICE ITS upgrade for LHC Run 3: commissioning in the laboratory

ALICE is the CERN LHC experiment optimised for the study of the strongly interacting matter produced in heavy-ion collisions and devoted to the characterisation of the quark-gluon plasma. To achieve the physics program for LHC Run 3, a major upgrade of the experimental apparatus is ongoing. A key element of the upgrade is the substitution of the Inner Tracking System (ITS) with a completely new silicon-based detector whose features will allow the reconstruction of rare physics channels, not accessible with the previous layout. The enabling technology for such a performance boost is the adoption of custom-designed CMOS MAPS as detecting elements. The installation of the detector in the ALICE cavern is completed and few months of commissioning will allow the final integration into the central systems. In this talk, an overview of the adopted technologies as well as the status of the detector commissioning will be given.

Monte Carlo simulation of charge collection processes in Monolithic Active Pixel Sensors for the ALICE ITS upgrade

Abstract A precise simulation of the response of Monolithic Active Pixel Sensors (MAPS) is difficult to achieve because of the difficulty in describing the charge collection process both in the epitaxial layer, a typically only partially depleted active volume, and in the substrate, a low resistivity bulk, of the sensor. Transient TCAD simulations provide good description of the electric field, but are too slow to be used in the simulation and analysis chain of HEP experiments. Therefore a faster simulation of the sensor response is necessary in order to provide in-depth understanding of the detector response. A fast tool developed to model the response of ALPIDE, the MAPS for the upgrade of the ALICE Inner Tracking System (ITS), is presented in this paper. The basic concept is a first principles Monte Carlo (MC) simulation, using the electric fields extracted from a TCAD simulation to model the drift of the charge carriers. That is, the more complex part of the simulation is handled by TCAD while preserving the speed of the MC simulation with only one free parameter — the external electric field strength. The tool is versatile, any MAPS architecture can be simulated once the proper external electric field is provided, and in this paper it has been done for two chips, developed for the ALICE ITS upgrade, INVESTIGATOR (analogue output) and ALPIDE (digital output). It will be shown that an excellent agreement between data and simulation has been achieved, both for 55Fe X-rays and minimum ionising particles.

The upgrade of the ALICE Inner Tracking System

The Inner Tracking System (ITS) of the ALICE experiment will be upgraded during the second long LHC shutdown in 2019–2020. The main goal of the ALICE ITS upgrade is to enable high precision measurements of low-momentum particles (<1 GeV/c) by acquiring a large sample of events, benefiting from the increase of the LHC instantaneous luminosity of Pb-Pb collisions to ℒ = 6 ⋅ 1027 cm−2 s−1 during Run 3. Working in this direction the ITS upgrade project is focusing on the increase of the readout rate, on the improvement of the impact parameter resolution, as well as on the improvement of the tracking efficiency and the position resolution. The major setup modification is the substitution of the current ITS with seven layers of silicon pixel detectors. The ALPIDE chip, a CMOS Monolithic Active Pixel Sensor (MAPS), was developed for this purpose and offers a spatial resolution of 5 μm. The use of MAPS together with a stringent mechanical design allows for the reduction of the material budget down to 0.35% X0 for the innermost layers and 1% X0 for the outer layers. The detector design was validated during the research and development period through a variety of tests ensuring the proper operation for the full lifetime inside ALICE. The production phase is close to completion with all the new assembled components undergoing different tests that aim to characterize the modules and staves and determine their qualification level. This contribution describes the detector design, the measurements performed during the research and development phase, as well as the production status.

ALPIDE: the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

The upgrade of the ALICE vertex detector, the Inner Tracking System (ITS), is scheduled to be installed during the next long shutdown period (2019-2020) of the CERN Large Hadron Collider (LHC) . The current ITS will be replaced by seven concentric layers of Monolithic Active Pixel Sensors (MAPS) with total active surface of ∼10 m2, thus making ALICE the first LHC experiment implementing MAPS detector technology on a large scale. The ALPIDE chip, based on TowerJazz 180 nm CMOS Imaging Process, is being developed for this purpose. A particular process feature, the deep p-well, is exploited so the full CMOS logic can be implemented over the active sensor area without impinging on the deposited charge collection. ALPIDE is implemented on silicon wafers with a high resistivity epitaxial layer. A single chip measures 15 mm by 30 mm and contains half a million pixels distributed in 512 rows and 1024 columns. In-pixel circuitry features amplification, shaping, discrimination and multi-event buffering. The readout is hit driven i.e. only addresses of hit pixels are sent to the periphery. The upgrade of the ITS presents two different sets of requirements for sensors of the inner and of the outer layers due to the significantly different track density, radiation level and active detector surface. The ALPIDE chip fulfils the stringent requirements in both cases. The detection efficiency is higher than 99%, fake-hit probability is orders of magnitude lower than the required 10−6 and spatial resolution within the required 5 μm. This performance is to be maintained even after a total ionising does (TID) of 2.7 Mrad and a non-ionising energy loss (NIEL) fluence of 1.7 × 1013 1 MeV neq/cm2, which is above what is expected during the detector lifetime. Readout rate of 100 kHz is provided and the power density of ALPIDE is less than 40 mW/cm2. This contribution will provide a summary of the ALPIDE features and main test results.

Radiation hard analog circuits for ALICE ITS upgrade

The ALICE experiment is planning to upgrade the ITS (Inner Tracking System) [1] detector during the LS2 shutdown. The present ITS will be fully replaced with a new one entirely based on CMOS monolithic pixel sensor chips fabricated in TowerJazz CMOS 0.18 μ m imaging technology. The large (3 cm × 1.5 cm = 4.5 cm2) ALPIDE (ALICE PIxel DEtector) sensor chip contains about 500 Kpixels, and will be used to cover a 10 m2 area with 12.5 Gpixels distributed over seven cylindrical layers. The ALPOSE chip was designed as a test chip for the various building blocks foreseen in the ALPIDE [2] pixel chip from CERN. The building blocks include: bandgap and Temperature sensor in four different flavours, and LDOs for powering schemes. One flavour of bandgap and temperature sensor will be included in the ALPIDE chip. Power consumption numbers have dropped very significantly making the use of LDOs less interesting, but in this paper all blocks are presented including measurement results before and after irradiation with neutrons to characterize robustness against displacement damage.

Upgrade of the ALICE Inner Tracking System

ALICE detector was constructed to study the properties of hot and dense hadronic matter formed in relativistic nuclear collisions. During the second long LHC shutdown in 2019-2020, the collaboration plans to upgrade the current vertex detector, the Inner Tracking System (ITS), in order to increase the reconstruction accuracy of secondary vertices and to lower the threshold of particle transverse momentum measurement. The upgrade strategy of ITS is based on the application of new Monolithic Active Pixel Sensors (MAPS) designed in 0.18 μm CMOS technology. The 50 μm thick chip consists of a single silicon die incorporating a 0.18 μm high-resistivity silicon epitaxial layer (sensor active volume) and matrix of charge collection diodes (pixels) with readout electronics. Radiation hardness of the upgraded ITS is one of the crucial moments in the overall performance of the system. A wide set of MAPS structures with different read-out circuits was produced and is being studied by the ALICE collaboration to optimize the pixel sensor functionality. An overview of the ALICE ITS upgrade and the expected performance improvement will be presented together with selected results from a campaign that includes several irradiation and beam tests.

MAPS development for the ALICE ITS upgrade

Monolithic Active Pixel Sensors (MAPS) offer the possibility to build pixel detectors and tracking layers with high spatial resolution and low material budget in commercial CMOS processes. Significant progress has been made in the field of MAPS in recent years, and they are now considered for the upgrades of the LHC experiments. This contribution will focus on MAPS detectors developed for the ALICE Inner Tracking System (ITS) upgrade and manufactured in the TowerJazz 180 nm CMOS imaging sensor process on wafers with a high resistivity epitaxial layer. Several sensor chip prototypes have been developed and produced to optimise both charge collection and readout circuitry. The chips have been characterised using electrical measurements, radioactive sources and particle beams. The tests indicate that the sensors satisfy the ALICE requirements and first prototypes with the final size of 1.5 × 3 cm2 have been produced in the first half of 2014. This contribution summarises the characterisation measurements and presents first results from the full-scale chips.

Design and characterization of novel monolithic pixel sensors for the ALICE ITS upgrade

Within the R&D activities for the upgrade of the ALICE Inner Tracking System (ITS), Monolithic Active Pixel Sensors (MAPS) are being developed and studied, due to their lower material budget (~0.3%X0 in total for each inner layer) and higher granularity (~20μm×20μm pixels) with respect to the present pixel detector. This paper presents the design and characterization results of the Explorer0 chip, manufactured in the TowerJazz 180nm CMOS Imaging Sensor process, based on a wafer with high-resistivity (ρ>1kΩcm) and 18μm thick epitaxial layer. The chip is organized in two sub-matrices with different pixel pitches (20μm and 30μm), each of them containing several pixel designs. The collection electrode size and shape, as well as the distance between the electrode and the surrounding electronics, are varied; the chip also offers the possibility to decouple the charge integration time from the readout time, and to change the sensor bias. The charge collection properties of the different pixel variants implemented in Explorer0 have been studied using a 55Fe X-ray source and 1–5GeV/c electrons and positrons. The sensor capacitance has been estimated, and the effect of the sensor bias has also been examined in detail. A second version of the Explorer0 chip (called Explorer1) has been submitted for production in March 2013, together with a novel circuit with in-pixel discrimination and a sparsified readout. Results from these submissions are also presented.

Charged particle detection performances of CMOS pixel sensors produced in a [formula omitted] process with a high resistivity epitaxial layer

The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50μm thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35μm CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz0.18μm CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1MRad and 1013neq/cm2 was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15°C to 30°C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz0.18μm CMOS process for the ALICE ITS upgrade.