Abstract
Monolithic Active Pixel Sensors (MAPS) offer the possibility to build pixel detectors and tracking layers with high spatial resolution and low material budget in commercial CMOS processes. Significant progress has been made in the field of MAPS in recent years, and they are now considered for the upgrades of the LHC experiments. This contribution will focus on MAPS detectors developed for the ALICE Inner Tracking System (ITS) upgrade and manufactured in the TowerJazz 180 nm CMOS imaging sensor process on wafers with a high resistivity epitaxial layer. Several sensor chip prototypes have been developed and produced to optimise both charge collection and readout circuitry. The chips have been characterised using electrical measurements, radioactive sources and particle beams. The tests indicate that the sensors satisfy the ALICE requirements and first prototypes with the final size of 1.5 × 3 cm2 have been produced in the first half of 2014. This contribution summarises the characterisation measurements and presents first results from the full-scale chips.
Highlights
Three chip architectures are under development for the ALICE Inner Tracking System (ITS) upgrade
The integration time is defined by the front-end shaping time and it is decoupled from the readout time
As expected the signal charge increases with increasing epi-layer thickness, but it was found to spread over too many pixels for thicknesses larger than 30 μm because the epi-layer is not fully depleted [9]
Summary
Three chip architectures are under development for the ALICE ITS upgrade. MISTRAL and ASTRAL are based on a rolling shutter readout structure. The difference between them is that MISTRAL uses an end-of-column discriminator, while ASTRAL uses an in-pixel discriminator [5]. In the ALPIDE (ALice PIxel DEtector) architecture, a low power binary front-end (40 nW) is combined with a data-driven readoPuitn,gtoYarendgu(cCeCtNheUp&owCeErRcNo)nsumption below 50 mW/cm. The integration time is defined by the front-end shaping time and it is decoupled from the readout time. The ALPIDE architecture aims for an integration time of 4 μs to reduce the pile up probability and a small readout time to increase the detector readout capability. This paper will concentrate on the ALPIDE development
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
