Aliasing Probabilities Research Articles

Determining Aliasing Probabilities in BIST by Counting Strings

The aliasing probability (AP) of a Built-In Self-Test (BIST) architecture is the probability that an error response gets classified as a good response. A general technique to determine the AP for many common and alternative BIST response analysis (RA) architectures is presented here. This technique models the RA circuit as a Deterministic Finite Automaton (DFA), and determines the AP by counting the ratio of strings accepted by the DFA to the total number of possible error strings. The strings accepted by a DFA can be calculated by counting the paths in the DFA‘s state transition graph (STG). Moreover, if the STG is complete, then the AP(k) = ((1/N)N^k-1)/(N^k-1), where k is the test length and N is the number of states and input symbols. This technique is demonstrated by determining the APs for the following RA architectures: Multiple-Input Shift Registers (MISRs), Cellular Automata (CA), Linear Feedback Shift Registers (LFSRs), accumulators, and a set of alternative architectures directly based on DFAs. This paper also shows how the adjacency matrix of the STG can be used to directly determine the AP of any RA architecture modeled as a DFA. Finally, the eigenvalues and eigenvectors of the DFA‘s STG adjacency matrix are used to derive general expressions for the DFA‘s AP.

Aliasing error for a mask ROM built-in self-test

To develop better ROM BIST techniques we first experimentally surveyed cell faults, word-line faults, bit-line faults, delay faults and other types of faults occurring in 1,000 faulty mask ROM chips. We found that most of the stuck-at faults were within a single mat. We then theoretically analyzed the aliasing probability for a mask ROM containing a fault or faults within a single mat. To experimentally evaluate BIST aliasing errors we implemented six MISRs on a custom board and observed actual aliasing errors. The experimentally measured aliasing probabilities agreed with the probabilities derived theoretically. No aliasing error occurred for the 16-stage, 8-input MISR.

On the maximum value of aliasing probabilities for single input signature registers

The aliasing error performance of a signature register is measured by the maximum values of the aliasing error probabilities for certain ranges of the bit-error rate (and those of the test length). Based on these measures, we evaluate the performances of all the single input signature registers whose feedback polynomials are primitive polynomials of degree 16 and generator polynomials of the double-error-correcting BCH codes of the same degree. When the degree of the feedback polynomial is large, say 32, it is computationally hard to obtain the exact aliasing probability. But we observe that the numbers of codewords with large weights in the corresponding code dominate the maximum value of the aliasing probabilities. By computing the numbers of codewords of large weights, we find primitive polynomials of degree 32 whose maximum value of the aliasing probabilities is very large for some test lengths. The error performance of an LFSR with any BCH polynomial of degree m for the test length 2/sup m/2/-2 is shown to be very good by deriving the formula for the weight distribution of the corresponding code. >

Aliasing properties of circular MISRs

In built-in self-test for logic circuits, test data reduction can be achieved using a linear feedback shift register. The probability of this data reduction allowing a faulty circuit to be declared good is the probability of aliasing. This article examines aliasing in circular multiple-input shift-registers (MISRs), under the independent bit error model. We present an exact closed form expression for aliasing probability without assuming equiprobable bit error probabilities. We show that the aliasing probability can be much larger than its asymptotic value. Irrespective of the register length we prove that for a circular MISR, when two inputs are used for testing out ofm possible inputs, high minimum spatial separations between inputs result in low aliasing probabilities. We also show that for equiprobable errors an m-bit circular MISR can be replaced with a set ofm single-bit MISRs without affecting aliasing probability or adding any additional logic, to reduce the propagation delay due to feedback path. The above features can be used as criteria for the MISR design.

Iterative algorithms for computing aliasing probabilities

An algorithm, ALG-MK, for computing exact aliasing probabilities in signature analysis is derived from a Markov process model of signature analysis. A previous algorithm, ALG-BL, which was derived from a Boolean expressions formulation of the problem, is reformulated so that it can also be reviewed as being based on a Markov process. Both algorithms compute exact aliasing probabilities in signature analysis. The computational complexities of the two models are compared. It is shown that the time complexity of the iterative algorithm ALG-MK is O(L2/sup k/), disregarding slight possible start-up and termination improvements, while that of ALG-BL is O(Lf2/sup k+f/), where k is the size of the signature register, f is the number of feedback taps, and L is the test sequence length. ALG-BL requires more shift and add operations, but requires half the number of floating-point multiplications that ALG-MK requires. The space complexity of ALG-MK is O(2/sup k/), while that of ALG-BL is O(2/sup k+f/). It is also shown that ALG-MK and ALG-BL are formally related through a linear transformation of their state vectors. Both algorithms may be used to study aliasing under generalized error models.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An analysis of the aliasing probability of multiple-input signature registers in the case of a 2/sup m/-ary symmetric channel

The aliasing probabilities of multiple-input signature registers (MISR) with m inputs for a 2/sup m/-ary symmetric channel, where each of the (2/sup m/-1) possible errors is equally likely, are analyzed. For this error model, the aliasing probabilities of MISRs are analyzed using the weight distributions of maximum-distance-separable (MDS) codes. The results show that the aliasing probabilities over the 2/sup m/-ary symmetric channel do not depend on the polynomials that characterize the MISRs. That is, for the 2/sup m/-ary symmetric channel, the aliasing probability of an MISR based on a primitive polynomial is exactly the same as one based on a nonprimitive one. In addition, it is observed that the aliasing probabilities, P/sub al/ (n), as a function of test length n, are monotonous for error probabilities p=0.2, 0.4, and 0.8. The aliasing probabilities of multiple MISRs based on Reed-Solomon codes are analyzed again for the 2/sup m/-ary symmetric channel, using the weight distributions of Reed-Solomon codes, which are MDS codes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis of Fault Detection Probability of CMOS Combinational Circuits and Its Application to Signature Testing

AbstractThis paper analyzes the rough behavior of aliasing probabilities (missing faults) when the signature testing is applied to CMOS combinational circuits. In the analysis of aliasing probabilities, the fault detection probability for one‐digit test patterns—the fault detection probability—becomes important. However, for general circuits it is difficult to evaluate the fault detection probability.In this paper the circuits are restricted to CMOS combinational circuits, and it is intended for the control circuits for microprocessors. For CMOS logic LSI's, the utilization of combinational gates follows a certain specific frequency and the expected value of the fault detection probability can be calculated.First, the gate usage frequencies are examined for three types of CMOS logic LSI's. Next, the fault detection probabilities of single gates are analyzed. Based on the forementioned results, the fault detection probabilities of simplified κ‐stage combinational circuits are analyzed. As a result, the expected value of the fault detection probability for a CMOS combinational circuit is shown to be 0.4 – 0.5. Using this expected value, the approximate behaviors of the aliasing probabilities for the signature testing are presented for MISR's and single‐input LFSR's applied to CMOS combinational circuits. In particular, for single‐input LFSR's it is shown that within the range of practical use, the aliasing probabilities are not monotonic.