Aliasing properties of circular MISRs

Abstract

In built-in self-test for logic circuits, test data reduction can be achieved using a linear feedback shift register. The probability of this data reduction allowing a faulty circuit to be declared good is the probability of aliasing. This article examines aliasing in circular multiple-input shift-registers (MISRs), under the independent bit error model. We present an exact closed form expression for aliasing probability without assuming equiprobable bit error probabilities. We show that the aliasing probability can be much larger than its asymptotic value. Irrespective of the register length we prove that for a circular MISR, when two inputs are used for testing out ofm possible inputs, high minimum spatial separations between inputs result in low aliasing probabilities. We also show that for equiprobable errors an m-bit circular MISR can be replaced with a set ofm single-bit MISRs without affecting aliasing probability or adding any additional logic, to reduce the propagation delay due to feedback path. The above features can be used as criteria for the MISR design.