High-level Synthesis Algorithm Research Articles

Enhanced chimp optimization algorithm for high level synthesis of digital filters

The HLS of digital filters is a complex optimization task in electronic design automation that increases the level of abstraction for designing and scheming digital circuits. The complexity of this issue attracting the interest of the researcher and solution of this issue is a big challenge for the researcher. The scientists are trying to present the various most powerful methods for this issue, but keep in mind these methods could be trapped in the complex space of this problem due to own weaknesses. Due to shortcomings of these methods, we are trying to design a new framework with the mixture of the phases of the powerful approaches for high level synthesis of digital filters in this work. This modification has been done by merging the chimp optimizer with sine cosine functions. The sine cosine phases helped in enhancing the exploitation phase of the chimp optimizer and also ignored the local optima in the search area during the searching of new shortest paths. The algorithms have been applied on 23-standard test suites and 14-digital filters for verifying the performance of the algorithms. Experimental results of single and multi-objective functions have been compared in terms of best score, best maxima, average, standard deviation, execution time, occupied area and speed respectively. Furthermore, by analyzing the effectiveness of the proposed algorithm with the recent algorithms for the HLS digital filters design, this can be concluded that the proposed method dominates the other two methods in HLS digital filters design. Another prominent feature of the proposed system in addition to the stated enhancement, is its rapid runtime, lowest delay, occupied area and lowest power in achieving an appropriate response. This could greatly reduce the cost of systems with broad dimensions while increasing the design speed.

Dependency Graph-based High-level Synthesis for Maximum Instruction Parallelism

Performance optimization is an important goal for High-level Synthesis (HLS). Existing HLS scheduling algorithms are all based on Control and Data Flow Graph (CDFG) and will schedule basic blocks in sequential order. Our study shows that the sequential scheduling order of basic blocks is a big limiting factor for achievable circuit performance. In this article, we propose a Dependency Graph (DG) with two important properties for scheduling. First, DG is a directed acyclic graph. Thus, no loop breaking heuristic is needed for scheduling. Second, DG can be used to identify the exact instruction parallelism. Our experiment shows that DG can lead to 76% instruction parallelism increase over CDFG. Based on DG, we propose a bottom-up scheduling algorithm to achieve much higher instruction parallelism than existing algorithms. Hierarchical state transition graph with guard conditions is proposed for efficient implementation of such high parallelism scheduling. Our experimental results show that our DG-based HLS algorithm can outperform the CDFG-based LegUp and the state-of-the-art industrial tool Vivado HLS by 2.88× and 1.29× on circuit latency, respectively.

Enhancing the Reliability of MEDA Biochips Using IJTAG and Wear Leveling

A digital microfluidic biochip (DMFB) enables the miniaturization of immunoassays, point-of-care clinical diagnostics, DNA sequencing, and other laboratory procedures in biochemistry. A recent generation of biochips uses a micro-electrode-dot-array (MEDA) architecture, which provides fine-grained control of droplets and seamlessly integrates microelectronics and microfluidics using CMOS technology and a TSMC fabrication process. To ensure that bioassays are carried out on MEDA biochips efficiently, high-level synthesis algorithms have recently been proposed. However, as in the case of conventional DMFBs, microelectrodes are likely to fail when they are heavily utilized, and previous methods fail to consider reliability issues. In this article, we first present a new microelectrode cell (MC) design such that the droplet-sensing operation can be enabled/disabled for individual MCs. Next, “partial update” and “partial sensing” operations are presented based on an IEEE Std. 1687 IJTAG network design. Finally, wear-leveling synthesis method is proposed to ensure uniform utilization of MCs on MEDA. A comprehensive set of simulation results demonstrate the effectiveness of the proposed hardware design and design automation methods.

Entropy-Directed Scheduling for FPGA High-Level Synthesis

High-level synthesis (HLS) is important for compiling an application design onto field-programmable gate array (FPGA) but still faces challenges of balancing scalability and quality of results in the scheduling process. In this article, we propose an entropy-directed scheduling (EDS) algorithm that efficiently generates high-quality schedules for FPGA HLS. This article is novel in three ways. First, we make the first attempt to adopt entropy in the scheduling of HLS, which is an intuitive and robust measurement with lots of good analytic properties. Second, we creatively leverage the maximum entropy principle to describe the scheduling process, which is proved equivalent to the optimal solution in some particular cases. Third, we make EDS automatically analyze the input graph structure and leverage a three-stage scheduling process to obtain high-quality results. As a result, EDS has the lowest time complexity among existing scheduling algorithms and is flexible to solve both latency- and resource-constrained problems while satisfying other constraints. The experimental results show that for latency-constrained scheduling problem, EDS reduces up to 68% resource usage and is $294\times $ faster than the force-directed scheduling algorithm. For resource-constrained scheduling problem, EDS obtains near-optimal solutions with an average speedup of 16 $410\times $ compared with ILP. To our best knowledge, this is the first EDS algorithm for FPGA HLS.

A Timing-driven Binding Algorithm for High-Level Synthesis of Three-dimensional Integrated Circuits

A Timing-driven Binding Algorithm for High-Level Synthesis of Three-dimensional Integrated Circuits

Design of retimed digital filters using MCM methodology for noise removal in EEG

High level synthesis of digital signal processing (DSP) systems converts the abstract behavioural specification in to register transfer level (RTL) description. The main objective of high level synthesis algorithms is to generate structure that satisfies various design constraints such as area, power and operating frequency. A modified MCM-based retiming algorithm is designed in this paper for DSP block optimisation. This is achieved by two ways in the present work. Firstly, pipelining and retiming is used as a high level synthesis optimisation methodology which can increase the operating frequency in sequential circuits such as digital filters. As the next step, MCM can be used to find the optimal solution for digital filters that gives implementation consisting of minimal number of shifters and adders/subtractors for a given constant co-efficient set. Electro-encephalography (EEG) is considered as an application in this work which requires sophisticated filters in removing the power noise and random noise introduced during the recording process.

Design of retimed digital filters using MCM methodology for noise removal in EEG

High level synthesis of digital signal processing (DSP) systems converts the abstract behavioural specification in to register transfer level (RTL) description. The main objective of high level synthesis algorithms is to generate structure that satisfies various design constraints such as area, power and operating frequency. A modified MCM-based retiming algorithm is designed in this paper for DSP block optimisation. This is achieved by two ways in the present work. Firstly, pipelining and retiming is used as a high level synthesis optimisation methodology which can increase the operating frequency in sequential circuits such as digital filters. As the next step, MCM can be used to find the optimal solution for digital filters that gives implementation consisting of minimal number of shifters and adders/subtractors for a given constant co-efficient set. Electro-encephalography (EEG) is considered as an application in this work which requires sophisticated filters in removing the power noise and random noise introduced during the recording process.

A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

An Optimized Scheduling Algorithm for High Level Synthesis (HLS) to Reduce the Control Steps

In Static List Scheduling (SLS), initially the ALAP (As Late As Possible) algorithm is performed, followed by ASAP (As Soon As Possible) algorithm. The time interval for control steps and successor selection are the vital drawback of ASAP algorithm. Hence, in this paper, the optimized scheduling algorithm is proposed for High Level Synthesis (HLS), where the ALAP in SLS is followed by Force Directed Scheduling (FDS). The proposed scheduling algorithm is implemented in Icarus Verilog and targeted in ZC7020 FPGA board. The proposed optimized scheduling algorithm is evaluated in terms of control steps and resource utilization. The evaluation is carried out for various benchmarks such as, EW Filter, IIR filter, FIR filter, AR filter and Discrete Cosine Transform (DCT). The achieved results in terms of the control steps and resource utilization (i.e. LUT and Flip-flop) shows the proposed optimized scheduling algorithm outperforms the conventional Static List Scheduling (SLS) algorithm.

A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures

A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures

Cyber–Physical Codesign at the Functional Level for Multidomain Automotive Systems

Software-integrated multidomain automotive systems, which is also referred to as automotive cyber–physical systems (CPS) consist of various interacting domains (software, hardware, multiphysics, communication, etc.). Design decisions in one domain may completely change the constraints and requirements in the other domains, e.g., adding more functions in a modern automotive CPS may require changes to thousands of lines of software code or even the mechanical architecture. Existing CPS design methodologies are siloed in a specific domain and therefore have limited design space exploration capabilities because only one domain can be tested at a time. This paper presents a functional-level cyber–physical codesign methodology starting from the functional model of the CPS capable of concurrently expressing (multi-)physics and control in automotive applications. Moreover, we introduce a high-level synthesis algorithm capable of selecting a set of optimized system architectures using various executable simulation components and cost metrics. We demonstrate our methodology with a realistic automotive use case and explore various design alternatives for implementing the control systems in pure continuous domain (e.g., traditional automotive subsystems without engine control units) or hybrid domain (e.g., brake-by-wire, steer-by-wire, drive-by-wire, etc.) under power, performance, and reliability constraints.

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design

In this paper, we first propose an HDR-mcd architecture, which integrates periodically all-in-phase based multiple clock domains and multi-cycle interconnect communication into high-level synthesis. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay should be considered during high-level synthesis. Next, we propose a high-level synthesis algorithm for HDR-mcd, which can reduce energy consumption by optimizing configuration and placement of huddles. Experimental results show that the proposed method achieves 32.5% energy-saving compared with the existing single clock domain based methods.

A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs

Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same.

A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures

Finite impulse response (FIR) filtering is a ubiquitous operation in digital signal processing systems and is generally implemented in full custom circuits due to high-speed and low-power design requirements. The complexity of an FIR filter is dominated by the multiplication of a large number of filter coefficients by the filter input or its time-shifted versions. Over the years, many high-level synthesis algorithms and filter architectures have been introduced in order to design FIR filters efficiently. This article reviews how constant multiplications can be designed using shifts and adders/subtractors that are maximally shared through a high-level synthesis algorithm based on some optimization criteria. It also presents different forms of FIR filters, namely, direct, transposed, and hybrid and shows how constant multiplications in each filter form can be realized under a shift-adds architecture. More importantly, it explores the impact of the multiplierless realization of each filter form on area, delay, and power dissipation of both custom (ASIC) and reconfigurable (FPGA) circuits by carrying out experiments with different bitwidths of filter input, design libraries, reconfigurable target devices, and optimization criteria in high-level synthesis algorithms.

A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures

A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures

A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures

A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures

Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool

In the last two decades, many efficient algorithms and architectures have been introduced for the design of low-complexity bit-parallel multiple constant multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. On the other hand, little attention has been given to the digit-serial MCM design that offers alternative low-complexity MCM operations albeit at the cost of an increased delay. In this paper, we address the problem of optimizing the gate-level area in digit-serial MCM designs and introduce high-level synthesis algorithms, design architectures, and a computer-aided design tool. Experimental results show the efficiency of the proposed optimization algorithms and of the digit-serial MCM architectures in the design of digit-serial MCM operations and finite impulse response filters.

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs

Design space exploration during high-level synthesis targets the computation of those design solutions which form optimal trade-off points. This quest for optimal trade-offs has been focused on studying the impact of various architectural-level parameters during high-level synthesis algorithms, silently neglecting the trade-offs produced from the combined impact of behavioral-level together with architectural-level parameters. We propose a novel design space, exploration methodology that studies an extended instance of the solution space considering the effects of combining compiler- and architectural-level transformations. It is shown that exploring the design space in a global manner reveals new trade-off points, thus shifting towards higher quality design solutions. We use a combination of upper-bounding conditions together with gradient-based heuristic pruning to efficiently traverse the extended search space. Our exploration framework delivers significant quality improvements without compromising the optimality (Pareto accuracy) of the discovered solutions, together with significant runtime reductions compared to exploring exhaustively the solution space at every allocation scenario.

A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation

A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation

Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages

Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages