An Optimized Scheduling Algorithm for High Level Synthesis (HLS) to Reduce the Control Steps

Abstract

In Static List Scheduling (SLS), initially the ALAP (As Late As Possible) algorithm is performed, followed by ASAP (As Soon As Possible) algorithm. The time interval for control steps and successor selection are the vital drawback of ASAP algorithm. Hence, in this paper, the optimized scheduling algorithm is proposed for High Level Synthesis (HLS), where the ALAP in SLS is followed by Force Directed Scheduling (FDS). The proposed scheduling algorithm is implemented in Icarus Verilog and targeted in ZC7020 FPGA board. The proposed optimized scheduling algorithm is evaluated in terms of control steps and resource utilization. The evaluation is carried out for various benchmarks such as, EW Filter, IIR filter, FIR filter, AR filter and Discrete Cosine Transform (DCT). The achieved results in terms of the control steps and resource utilization (i.e. LUT and Flip-flop) shows the proposed optimized scheduling algorithm outperforms the conventional Static List Scheduling (SLS) algorithm.