Algebraic Soft-decision Decoding Algorithms Research Articles

Efficient architecture for algebraic soft‐decision decoding of Reed–Solomon codes

Reed–Solomon (RS) codes possess excellent error correction capability. Algebraic soft-decision decoding (ASD) of RS codes can provide better correction performance than the hard-decision decoding (HDD). The low-complexity Chase (LCC) decoding has the lowest complexity cost and similar or even higher coding gain among all of the available ASD algorithms. Instead of employing complicated interpolation technique, the LCC decoding can be implemented based on the HDD. This study proposes a modified serial LCC decoder, which employs a novel syndrome calculation, polynomial selection, Chien search and Forney algorithm block. In addition, an improved two-dimensional optimisation is provided to reduce the hardware complexity of the proposed decoder. Compared with the previous design, the proposed decoder can improve about 1.27 times speed and obtain 1.29 times higher efficiency in terms of throughput-over-slice ratio.

Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified Syndrome Computation

Reed-Solomon (RS) codes are widely used in digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can obtain significant coding gain over the hard-decision decoding (HDD). Compared with other ASD algorithms, the low-complexity Chase (LCC) decoding algorithm needs less computation complexity with similar or higher coding gain. Besides employing complicated interpolation algorithm, the LCC decoding can also be implemented based on the HDD. However, the previous syndrome computation for 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">η</sup> test vectors and the key equation solver (KES) in the HDD requires long latency and remarkable hardware. In this brief, a unified syndrome computation algorithm and the corresponding architecture are proposed. Cooperating with the KES in the reduced inversion-free Berlekamp-Messy algorithm, the reduced-complexity LCC RS decoder can speed up by 57% and the area will be reduced to 62% compared with the original design for η = 3.

Low-power high-efficiency architecture for low-complexity chase soft-decision Reed–Solomon decoding

Algebraic soft-decision decoding (ASD) of Reed–Solomon (RS) codes can obtain significant coding gain over the hard-decision decoding with polynomial complexity. Compared with other ASD algorithms, the low-complexity chase (LCC) decoding testing 2η test vectors has less computation complexity with similar or better coding gain. To reduce the latency of the interpolation, one major step of the LCC decoding, multiple interpolators can be applied and the pipelined architecture is usually adopted to make the throughput of the decoder higher. However, for application specific integrated circuit (ASIC) implementation and practical applications, the area and power consumption of the pipelined decoder are not preferable. This study proposes a modified serial LCC decoder architecture which reduces the power consumption and hardware requirement while keeping the shortest critical path as one adder, one multiplexer and one multiplier. As major contributions of this study, a novel re-encoder and erasure decoder block and an improved way to compute syndromes are proposed to reduce the whole latency of the decoder. For a (458, 410) RS code over Galois Field (GF)(210) with η=8, the hardware requirement and power consumption of the proposed LCC decoder are reduced by 23 and 25% than those of the common pipelined counterparts, respectively.

Modified Low-Complexity Chase Soft-Decision Decoder of Reed–Solomon Codes

Reed---Solomon (RS) codes are widely used as error-correcting codes in digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can achieve substantial coding gain with polynomial complexity. Among practical ASD algorithms, the low-complexity chase (LCC) algorithm that tests 2 ? vectors can achieve similar or higher coding gain with lower complexity. For applications such as magnetic recording, the performance of the LCC decoding is degraded by the inter-symbol interference from the channel. Improving the performance of the LCC decoding requires larger ?, which leads to higher complexity. In this paper, a modified LCC (MLCC) decoding is proposed by adding erasures to the test vectors. With the same ?, the proposed algorithm can achieve much better performance than the original LCC decoding. One major step of the LCC and MLCC decoding is the interpolation. To reduce the complexity of the interpolation, this paper also proposed a prioritized interpolation scheme to test a small proportion of the vectors at a time, starting with the ones with higher reliabilities. For a (458, 410) RS code, by testing 1/8 of the vectors at a time, the area requirement of the MLCC decoder with ??=?8 can be reduced to 57%, and the average decoding latency is reduced to 73%.

High-Throughput Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding

Reed-Solomon (RS) codes are used as error-correcting codes in numerous digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can achieve substantial coding gain with polynomial complexity. Among practical ASD algorithms, the iterative bit-level generalized minimum distance (BGMD) decoding can achieve similar or higher coding gain with lower complexity. The interpolation is a major step of ASD. The maximum achievable speed of this step is limited by the inherent serial nature of the interpolation algorithm. In this paper, a novel interpolation scheme that is capable of combining multiple interpolation iterations, as well as sharing interpolation results from previous decoding iterations, is developed for the iterative BGMD decoding. In addition, efficient VLSI architectures are proposed to implement the developed scheme. Based on the proposed architectures, an interpolator for a (255, 239) RS code is implemented on field programmable gate array (FPGA) devices. On a Xilinx Virtex-II device, our interpolator can achieve a throughput of 440 Mbps, which is 64% higher than the fastest previous design, with 51% less FPGA resource.

Efficient VLSI Architecture for Soft-Decision Decoding of Reed–Solomon Codes

Reed-Solomon (RS) codes have very broad applications in digital communication and storage systems. The developed algebraic soft-decision decoding (ASD) algorithms of RS codes can achieve substantial coding gain with polynomial complexity. Among the ASD algorithms with practical multiplicity assignment schemes, the bit-level generalized minimum distance (BGMD) decoding algorithm can achieve similar or higher coding gain with lower complexity. ASD algorithms consist of two major steps: the interpolation and the factorization. In this paper, novel architectures for both steps are proposed for the BGMD decoder. The interpolation architecture is based on the newly proposed Lee-O'Sullivan (LO) algorithm. By exploiting the characteristics of the LO algorithm and the multiplicity assignment scheme in the BGMD decoder, the proposed interpolation architecture for a (255, 239) RS code can achieve 25% higher efficiency in terms of speed/area ratio than prior efforts. Root computation over finite fields and polynomial updating are the two main steps of the factorization. A low-latency and prediction-free scheme is introduced in this paper for the root computation in the BGMD decoder. In addition, novel coefficient storage schemes and parallel processing architectures are developed to reduce the latency of the polynomial updating. The proposed factorization architecture is 126% more efficient than the previous direct root computation factorization architecture.