Al2O3 Gate Dielectric Films Research Articles

Fully Ion Implanted Normally-Off GaN DMOSFETs with ALD-Al2O3 Gate Dielectrics

A normally-off GaN double-implanted vertical MOSFET (DMOSFET) with an atomic layer deposition (ALD)-Al2O3 gate dielectric film on a free-standing GaN substrate fabricated by triple ion implantation is presented. The DMOSFET was formed with Si ion implanted source regions in a Mg ion implanted p-type base with N ion implanted termination regions. A maximum drain current of 115 mA/mm, maximum transconductance of 19 mS/mm at a drain voltage of 15 V, and a threshold voltage of 3.6 V were obtained for the fabricated DMOSFET with a gate length of 0.4 μm with an estimated p-type base Mg surface concentration of 5 × 1018 cm−3. The difference between calculated and measured Vths could be due to the activation ratio of ion-implanted Mg as well as Fermi level pinning and the interface state density. On-resistance of 9.3 mΩ·cm2 estimated from the linear region was also attained. Blocking voltage at off-state was 213 V. The fully ion implanted GaN DMOSFET is a promising candidate for future high-voltage and high-power applications.

Physisorbed-precursor-assisted atomic layer deposition of reliable ultrathin dielectric films on inert graphene surfaces for low-power electronics

Among the most fundamental challenges encountered in the successful incorporation of graphene in silicon-based electronics is the conformal growth of ultrathin dielectric films, especially those with thicknesses lower than 5 nm, on chemically inert graphene surfaces. Here, we present physisorbed-precursor-assisted atomic layer deposition (pALD) as an extremely robust method for fabricating such films. Using atomic-scale characterisation, it is confirmed that conformal and intact ultrathin Al2O3 films can be synthesised on graphene by pALD. The mechanism underlying the pALD process is identified through first-principles calculations based on density functional theory. Further, this novel deposition technique is used to fabricate two types of wafer-scale devices. It is found that the incorporation of a 5 nm-thick pALD Al2O3 gate dielectric film improves the performance of metal-oxide-graphene field-effect transistors to a greater extent than does the incorporation of a conventional ALD Al2O3 film. We also employ a 5 nm-thick pALD HfO2 film as a highly scalable dielectric layer with a capacitance equivalent oxide thickness of 1 nm in graphene-based tunnelling field-effect transistors fabricated on a glass wafer and achieve a subthreshold swing of 30 mV/dec. This significant improvement in switching allows for the low-voltage operation of an inverter within 0.5 V of both the drain and the gate voltages, thus paving the way for low-power electronics.

12.5 A/350 V AlGaN/GaN‐on‐Si MOS‐HEMT with low specific on‐resistance and minimal threshold hysteresis

An AlGaN/GaN metal-oxide semiconductor (MOS) high-electron mobility transistor (HEMT) on silicon substrate was obtained with 8 nm Al2O3 gate dielectric films grown using atomic layer deposition. The MOS-HEMT shows a low specific on-resistance of 0.57 Omega.mm(2), a large maximum saturate drain current of 12.5 A and a minimal threshold hysteresis of 0.05 V. Low specific on-resistance, large maximum saturate drain current and minimal threshold hysteresis show that the fabricated MOS-HEMT is very suitable for power switching applications.

Depletion-mode Ga2O3 metal-oxide-semiconductor field-effect transistors on β-Ga2O3 (010) substrates and temperature dependence of their device characteristics

Single-crystal gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors were fabricated on a semi-insulating β-Ga2O3 (010) substrate. A Sn-doped n-Ga2O3 channel layer was grown by molecular-beam epitaxy. Si-ion implantation doping was performed to source and drain electrode regions for obtaining low-resistance ohmic contacts. An Al2O3 gate dielectric film formed by atomic layer deposition passivated the device surface and significantly reduced gate leakage. The device with a gate length of 2 μm showed effective gate modulation of the drain current with an extremely low off-state drain leakage of less than a few pA/mm, leading to a high drain current on/off ratio of over ten orders of magnitude. A three-terminal off-state breakdown voltage of 370 V was achieved. Stable transistor operation was sustained at temperatures up to 250 °C.

High-performance ZnO thin-film transistor fabricated by atomic layer deposition

We report the fabrication and characteristics of a ZnO thin-film transistor (TFT) using a 50 nm thick ZnO film as an active layer on an Al2O3 gate dielectric film deposited by atomic layer deposition. Lowering the deposition temperature allowed the control of the carrier concentration of the active channel layer (ZnO film) in the TFT device. The ZnO TFT fabricated at 110 °C exhibited high-performance TFT characteristics including a saturation field-effect mobility of 11.86 cm2 V−1 s−1, an on-to-off current ratio of 3.09 × 107 and a sub-threshold gate-voltage swing of 0.72 V decade−1.

Effect of chemical surface treatments on interfacial and electrical characteristics of atomic-layer-deposited Al2O3 films on Ge substrates

The Ge surfaces were cleaned and passivated by two kinds of chemical pretreatments: conventional combination of HF+(NH4)2S, and new one of HBr+(NH4)2S. The chemical states and stability at passivated Ge surfaces were carefully characterized. The influence of chemical surface treatments on the interface and electrical properties of Al2O3 gate dielectric films on Ge grown by atomic layer deposition (ALD) has been investigated deeply. It is found that the combination of HBr and (NH4)2S can remove more Ge–O bonds on the Ge surface compared to that of conventional HF and (NH4)2S with excellent stability. X-ray photoelectron spectroscopy (XPS) reveals that HBr and (NH4)2S treated Ge surface has a mixture states of GeOx (9.25%) and GeS (7.40%) while HF and (NH4)2S treated Ge surface has a mixture states of GeOx (16.45%) and GeS (3.37%). And the Ge–S peak from the surface of Ge substrates decreases a little after the HBr and (NH4)2S treated Ge surface was exposed in the ambient for 300min, which suggests the Ge surface is stable to oxidants. The Al2O3 films on HBr and (NH4)2S treated Ge substrates exhibits better electrical properties such as large capacitance, decreased leakage current density by ∼two orders of magnitude, and less C–V hysteresis. This indicates that a reduction in charge traps possibly at the interface and more interface traps are terminated by sulfur. The surface treatment of HBr and (NH4)2S seems to be very promising in improving the quality of high-k gate stack on Ge substrates.

Electrical performance of Al2O3 gate dielectric films deposited by atomic layer deposition on 4H-SiC

Stoichiometric and pure Al2O3 gate dielectric films were grown on n-type 4H-SiC by a thermal atomic layer deposition process. The electrical properties of both amorphous and epitaxial Al2O3 films were studied by capacitance-voltage and current-voltage measurements of metal-oxide-semiconductor capacitors. A dielectric constant of 9 and a flatband voltage shift of +1.3V were determined. A leakage current density of 10−3A∕cm2 at 8MV∕cm was obtained for the amorphous Al2O3 films, lower than that of any high-κ gate oxide on 4H-SiC reported to date. A Fowler-Nordheim tunneling mechanism was used to determine an Al2O3∕4H-SiC barrier height of 1.58eV. Higher leakage current was obtained for the epitaxial γ-Al2O3 films, likely due to grain boundary conduction.

Performance Improvement of Ultralow Temperature Polycrystalline Silicon TFT on Plastic Substrate by Plasma Oxidation of Polycrystalline Si Surface

The thin-film transistor (TFT) performances were enhanced and stabilized by the plasma oxidation of the polycrystalline Si surface prior to the plasma enhanced atomic layer deposition of an Al2O3 gate dielectric film. The authors attribute this improvement to the formation of a high-quality oxide interface layer between the gate dielectric film and the poly-Si film. The interface oxide has a predominant effect on the TFT's characteristics and is regulated by the plasma oxidation temperature and the gap distance between the electrode and polycrystalline Si surface

Thermal annealing effects on the structure and electrical properties of Al[sub 2]O[sub 3] gate dielectrics on fully depleted SiGe on insulator

The interfacial characteristics and electrical properties of as-deposited and annealed Al2O3 gate dielectric films fabricated on fully depleted SiGe on insulator are investigated. The surface morphology of the gate dielectric is observed by atomic force microscopy, and its physical thickness and structure are determined by high-resolution transmission electron microscopy. Assessment of the energy shifts of the interfacial components observed by high-resolution x-ray photoelectron spectroscopy shows that oxidation of Ge occurs readily at the growth temperature, leading to a mixture of Si and Ge oxides at the Al2O3∕SiGe interface. After annealing, the relative intensity of GeOx diminishes significantly, whereas the relative intensity of the Si suboxides or SiO2 increases, and especially, the formation of silicate is observed. The chemical state changes in the interfacial layer affect the flatband voltage (Vfb) and the density of the interfacial states.

Impact of moisture on charge trapping and flatband voltage in Al2O3 gate dielectric films

High permittivity gate dielectric films exhibit significant charge trapping during electrical stressing. In this letter, the impact of low temperature postmetallization anneals on charge trapping in Al2O3 films is reported; anneals were performed in vacuum and forming gas ambient. These anneals not only reduce charge trapping but also move the flatband voltage towards an ideal value that corresponds to the difference in work function. Based on these experiments, it is concluded that absorbed moisture in the films provides hydrogen that concomitantly reduces charge trapping and fixed charge densities in Al2O3 films.

Measurement of barrier heights in high permittivity gate dielectric films

Based on theoretical studies of tunneling current phenomenon, a method for measuring barrier heights in metal–oxide–semiconductor structures is illustrated. Using this method, barrier heights associated with the Al2O3 gate dielectric films are investigated. Also, the main conduction mechanism in Al2O3 gate dielectric films is identified to be tunneling.

Reliability of MIS transistors with plasma deposited Al2O3 gate dielectric film

Reliability of MIS transistors with plasma deposited Al2O3 gate dielectric film