Al2O3 Capping Layer Research Articles

Passivation effect on gate-bias stress instability of carbon nanotube thin film transistors

A prior requirement of any developed transistor for practical use is the stability test. Random network carbon nanotube-thin film transistor (CNT-TFT) was fabricated on SiO2/Si. Gate bias stress stability was investigated with various passivation layers of HfO2 and Al2O3. Compared to the threshold voltage shift without passivation layer, the measured values in the presence of passivation layers were reduced independent of gate bias polarity except HfO2 under positive gate bias stress (PGBS). Al2O3 capping layer was found to be the best passivation layer to prevent ambient gas adsorption, while gas adsorption on HfO2 layer was unavoidable, inducing surface charges to increase threshold voltage shift in particular for PGBS. This high performance in the gate bias stress test of CNT-TFT even superior to that of amorphous silicon opens potential applications to active TFT industry for soft electronics.

Top gating of epitaxial (Bi1−xSbx)2Te3 topological insulator thin films

The tunability of the chemical potential for a wide range encompassing the Dirac point is important for many future devices based on topological insulators. Here, we report a method to fabricate highly efficient top gates on epitaxially grown (Bi1−xSbx)2Te3 topological insulator thin films without degrading the film quality. By combining an in situ deposited Al2O3 capping layer and a SiNx dielectric layer deposited at low temperature, we were able to protect the films from degradation during the fabrication processes. We demonstrate that by using this top gate, the carriers in the top surface can be efficiently tuned from n- to p-type. We also show that magnetotransport properties give evidence for decoupled transport through top and bottom surfaces for the entire range of gate voltage, which is only possible in truly bulk-insulating samples.

Effect of ultrathin GeOx interfacial layer formed by thermal oxidation on Al2O3 capped Ge

We propose a modified thermal oxidation method in which an Al2O3 capping layer is used as an oxygen blocking layer (OBL) to form an ultrathin GeOx interfacial layer, and obtain a superior Al2O3/GeOx/Ge gate stack. The GeOx interfacial layer is formed in oxidation reaction by oxygen passing through the Al2O3 OBL, in which the Al2O3 layer could restrain the oxygen diffusion and suppress the GeO desorption during thermal treatment. The thickness of the GeOx interfacial layer would dramatically decrease as the thickness of Al2O3 OBL increases, which is beneficial to achieving an ultrathin GeOx interfacial layer to satisfy the demand for small equivalent oxide thickness (EOT). In addition, the thickness of the GeOx interfacial layer has little influence on the passivation effect of the Al2O3/Ge interface. Ge (100) p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) using the Al2O3/GeOx/Ge gate stacks exhibit excellent electrical characteristics; that is, a drain current on-off (Ion/Ioff) ratio of above 1×104, a subthreshold slope of ∼ 120 mV/dec, and a peak hole mobility of 265 cm2/V·s are achieved.

Passivation of n$^{+}$-Type Si Surfaces by Low Temperature Processed SiO$_{2}$/Al$_{2}$O$_{3}$ Stacks

The surface passivation of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> stacks prepared at low process temperatures was investigated on phosphorous diffused n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -type Si surfaces with a broad range of sheet resistances. Two kinds of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> films were prepared, the first with plasma-enhanced chemical vapor deposition (PECVD) and the second in a wet chemical process. After atomic layer deposition of the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping layer, the resulting SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> stacks differ in the polarity of their fixed charge density, i.e., the PECVD SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> stacks had a positive and the wet chemically grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> stacks a negative fixed charge density. The PECVD SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> stacks resulted in a high surface passivation over a broad range of sheet resistances whereas the wet chemically grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> stacks were only feasible for diffused surfaces with low sheet resistances (<; 100 Ω/□). By corona charging experiments, it was established that the field effect based on a negative fixed charge density was the reason for the loss in surface passivation in the specific range of diffused surfaces.

Fabrication and magnetic properties of FePt/Al2O3 composite film by atomic-layer-deposition

Self-assembled face-centered cubic FePt nanoparticles were capped by a amorphous Al2O3 capping layer with the thickness of 10nm using the atomic layer deposition (ALD) technology, and transmission electron microscopy indicates that the FePt nanocrystals are well-separated. After annealing the composite film at 700°C, well-monodispersed face-centered tetragonal FePt particles can be obtained, yielding a coercivity value Hc=5.9kOe with the magnetocrystalline anisotropy of 3.86MJ/m3. The thermal factor for the composite film is 68.5, meeting the industry requirement (KuV/kBT ≥ 50). The protection of amorphous Al2O3 matrix can effectively inhibit grain growth and particle aggregation, and preserve the ordered domains of FePt nanoparticles during the L10 ordering transition. The combination of ALD-capping layer and self-assembled FePt nanoparticles provides a new potential approach to fabricate patterned magnetic recording media with ultrahigh areal density.

Effect of Suppressing Reoxidation at SiO&lt;sub&gt;2&lt;/sub&gt;/SiC Interface during Post-Oxidation Annealing in N&lt;sub&gt;2&lt;/sub&gt;O with Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt; Capping Layer

In the present study, applying Al2O3 capping layer as suppressing layer of oxygen diffusion to SiC-MOS structures, we investigated the effect of Al2O3 layer as suppression of reoxidation at SiO2/SiC interface and decrease of Dit. We evaluated MOS capacitors which have SiO2/SiC and Al2O3/SiO2/SiC structure on 4H-SiC (0001) Si-face epitaxial wafers after post-oxidation anneal process (N2O:N2=1:9 [slm]) at temperatures ranging from 1000 °C to 1300 °C for 30min. The Al2O3/SiO2/SiC structure of reoxidation thickness, surface roughness and Dit are smaller than those of SiO2/SiC structure. These results show that the suppression of reoxidation during POA is important to improve the SiO2/SiC interfacial qualities.

Effect of Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt; Capping Layer in ZnO TFT Fabricated by Atomic Layer Deposition

In this paper, the electrical and physical analysis is carried out to investigate the effect of Al2O3 capping layer on ZnO film using atomic layer deposition. ZnO TFTs shows the metallic conduction behavior as Al2O3 capping layer thickness increases. From SIMS analysis, it is found out that the diffusion of Al into ZnO film is enhanced according to Al2O3 capping layer thickness. Moreover, the defects related to oxygen such as oxygen vacancy increase from XPS analysis and ZnO films reveal less compressive stress by substitution of Zn with Al form XRD analysis. That is, the metallic conduction behavior of ZnO TFTs with Al2O3 capping layer can be explained due to increase in the carrier concentration in ZnO channel layer from oxygen vacancy and substitution of Zn with Al.

Plasma-Assisted ALD for the Conformal Deposition of SiO2: Process, Material and Electronic Properties

Plasma-assisted atomic layer deposition (ALD) was used to deposit SiO2 films in the temperature range of Tdep = 50–400°C on Si(100). H2Si[N(C2H5)2]2 and an O2 plasma were used as Si precursor and oxidant, respectively. The ALD growth process and material properties were characterized in detail. Ultrashort precursor doses (∼50 ms) were found to be sufficient to reach self-limiting ALD growth with a growth-per-cycle of ∼1.2 Å (Tdep = ∼200°C) leading to SiO2 films with O/Si ratio of ∼2.1. Moreover, the plasma ALD process led to a high conformality (95–100%) for trenches with aspect ratios of ∼30. In addition, the electronic (interface) properties of ultrathin ALD SiO2 films and ALD SiO2/Al2O3 stacks were studied by capacitance-voltage and photoconductance decay measurements. The interface quality associated with SiO2 was improved significantly by using an ultrathin ALD Al2O3 capping layer and annealing. The interface defect densities decreased from ∼1×1012 eV−1 cm−2 (at mid gap) for single layer SiO2 to < 1011 eV−1 cm−2 for the stacks. Correspondingly, ultralow surface recombination velocities < 3 cm/s were obtained for n-type Si. The density and polarity of the fixed charges associated with the stacks were found to be critically dependent on the SiO2 thickness (1–30 nm).

Silicon Surface Passivation by Thin Thermal Oxide/PECVD Layer Stack Systems

For the passivation of p-type silicon surfaces, we investigate layer systems consisting of a thin layer of thermally grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and different dielectric capping layers deposited by means of plasma-enhanced chemical vapor deposition (PECVD). We find that the thermal SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer thickness strongly impacts the passivation quality and interface parameters of the stacks. Capacitance-voltage measurements reveal that for Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and SiN <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> capping layers, an increased thermal SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> film thickness suppresses charge formation at the interface between SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and the capping layer. Interface trap density and effective carrier lifetime data suggest that a certain thermal SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> thickness is required to achieve appropriate chemical passivation. The combination of a thin thermal SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer (~4 nm) and a PECVD-SiO <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> capping results in very low surface recombination velocities of a few centimeters per second, measured on p-type 1-Ω·cm float-zone silicon after contact firing and postmetallization annealing. The experimentally observed dependence of the surface recombination velocity on the fixed charge density, gate voltage, and injection density is reproduced very accurately by analytical calculations that use the measured interface trap density and total charge density at the Si/insulator interface. The model also includes additional recombination in the space charge region of inverted surfaces.

Al 2 O 3 / GeO x / Ge gate stacks with low interface trap density fabricated by electron cyclotron resonance plasma postoxidation

An electron cyclotron resonance (ECR) plasma postoxidation method has been employed for forming Al2O3/GeOx/Ge metal-oxide-semiconductor (MOS) structures. X-ray photoelectron spectroscopy and transmission electron microscope characterizations have revealed that a GeOx layer is formed beneath the Al2O3 capping layer by exposing the Al2O3/Ge structures to ECR oxygen plasma. The interface trap density (Dit) of Au/Al2O3/GeOx/Ge MOS capacitors is found to be significantly suppressed down to lower than 1011 cm−2 eV−1. Especially, a plasma postoxidation time of as short as 10 s is sufficient to reduce Dit with maintaining the equivalent oxide thickness (EOT). As a result, the minimum Dit values and EOT of 5×1010 cm−2 eV−1 and 1.67 nm, and 6×1010 cm−2 eV−1 and 1.83 nm have been realized for Al2O3/GeOx/Ge MOS structures with p- and n-type substrates, respectively.

Etch Behavior of ALD Al2O3 on HfSiO and HfSiON Stacks in Acidic and Basic Etchants

For the integration of advance gate stacks, selective wet etching of an Al2O3 capping layer on top of high-k dielectrics was studied. From the fundamental etch study on the single-layer Al2O3, HfSiO and HfSiON thin films were prepared by atomic layer deposition (ALD). Using the etch rate information of each single layer, several optimized etch conditions in acidic and basic etchants including H3PO4, NH4OH, and TMAH resulted in wet etch selectivities of Al2O3 to high-k materials higher than 50:1. As a result, the Al2O3 capping layer on Si/SiO2/high-k multi-layer gate stack could be completely removed without thinning of the underlying high-k thin films. Finally, the etch mechanisms of Al2O3 in acidic and basic etchants were studied and the etch rates of Al2O3 were determined as functions of [H+] and [OH−].

Enhancement of a-IZO TTFT Performance by Using Y[sub 2]O[sub 3]∕Al[sub 2]O[sub 3] Bilayer Dielectrics

A comparison study was performed on radio frequency sputtered amorphous In-Zn-O transparent thin-film transistors (a-IZO TTFTs) using Y2O3 and Y2O3/Al2O3 dielectrics. Y2O3 has strong affinity for water and carbon dioxide molecules present in the air, which would induce a great deal of Y-O center dot electron traps at the Y2O3/a-IZO interface and ruin the device performance eventually. It is proposed that an Al2O3 capping layer is utilized to avoid chemical reaction on the surface of Y2O3, then the detrimental effects that yield electron trap states are circumvented. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3519412] All rights reserved.

Excellent Si surface passivation by low temperature SiO2 using an ultrathin Al2O3 capping film

AbstractIt is demonstrated that the application of an ultrathin aluminum oxide (Al2O3) capping film can improve the level of silicon surface passivation obtained by low‐temperature synthesized SiO2 profoundly. For such stacks, a very high level of surface passivation was achieved after annealing, with Seff &lt; 2 cm/s for 3.5 Ω cm n‐type c‐Si. This can be attributed primarily to a low interface defect density (Dit &lt; 1011 eV–1 cm–2). Consequently, the Al2O3 capping layer induced a high level of chemical passivation at the Si/SiO2 interface. Moreover, the stacks showed an exceptional stability during high‐temperature firing processes and therefore provide a low temperature (≤400 °C) alternative to thermally‐grown SiO2. (© 2011 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

The VFB Modulation Effect of ALD Grown Al2O3, SrO, La2O3 Capping Layers with HfO2 Gate Dielectrics

The effect of atomic layer deposited Al2O3, SrO, and La2O3 capping layers with HfO2 gate dielectrics were examined ffor flat band voltage (VFB) modulation. Al2O3 capping layers cause a VFB shift into the positive voltage direction, while SrO and La2O3 capping layers cause a shift into the negative voltage direction. The bottom capping layer, which positions between the Si substrate and the HfO2 dielectric was more effective in modulating the VFB compared to the top capping layer. The insulating properties of the gate dielectric stacks with different capping layers were also examined. X-ray photoelectron spectroscopy analysis verified that top capping layers did not generally diffuse to the interface between the Si substrate and the HfO2 dielectrics, which supports the result that bottom capping layers are more effective in modulating the VFB.

Effects of an Al2O3 capping layer on La2O3 deposited by remote plasma atomic layer deposition

The physical and electrical properties of La2O3 with and without an Al2O3 capping layer deposited by remote plasma atomic layer deposition were investigated. The electrical properties of the La2O3 films degraded due to the formation of lanthanum hydroxide after being exposed to air. The results of x-ray photoemission spectroscopy showed that the quantity of OH groups absorbed increased after exposure to air. For La2O3 with an Al2O3 capping layer, however, the electrical properties of the film did not change substantially because the capping layer effectively suppressed the formation of lanthanum hydroxide. The capacitance of the La2O3 decreased more than 30% after exposure to air, while La2O3 with an Al2O3 capping layer decreased by only about 4%. The VFB value of the La2O3 with an Al2O3 capping layer was near zero, and the hysteresis was about 120 mV. The leakage current densities of the film were maintained below 5 × 10−7 A/cm2 up to −15 MV/cm and the effective breakdown field was about −23.5 MV/cm.

The distribution of chemical elements in Al- or La-capped high-κ metal gate stacks

The spatial distribution of chemical elements is studied in high-κ, metal-gated stacks applied in field effect transistors. Using the transmission electron microscope (TEM)-based analytical techniques electron energy-loss spectroscopy (EELS) and energy-dispersive x-ray spectroscopy, it is demonstrated that Al2O3 and La2O3 capping layers show distinctly different diffusion profiles. The importance of the EELS collection angle is discussed. Popular chemical distribution models that assume La-rich interface layers are rejected.

Wafer-Level Transfer Technologies for PZT-Based RF MEMS Switches

We report on wafer-level transfer technologies to integrate PZT-based radio frequency (RF) microelectromechanical-systems switches on CMOS. Such heterogeneous integration can overcome the incompatibility of PZT material with back-end-of-the-line (BEOL) CMOS technology. The PZT stack and the transfer process have been optimized to avoid degradation of the PZT actuators during the transfer. In particular, we have optimized the seed layer for the growth of highly oriented PZT on a patterned TiO2-Pt layer, optimized the electrodes structure, and developed an Al2O3 capping layer to prevent degradation of PZT during the transfer process. A full wafer-level transfer process and a selective transfer technology allowing the distribution of RF switches from one source wafer to many receiving wafers has been demonstrated. The latest transfer process demonstrated exhibits great potential for cost optimization of wafer-level transfer of microdevices. In a separate experiment, we have demonstrated the BEOL CMOS compatibility of our integration technique. Switch characterization showed insertion loss of less than 0.5 dB and an isolation better than 30 dB for the 0.4- to 6-GHz frequency range with 15-V actuation voltage.

Temperature Coefficient of Threshold Voltage in High-k Metal Gate Transistors with Various TiN and Capping Layer Thicknesses

The temperature coefficient of Vth (=dVth/dT), which is commonly utilized for circuit design, was systematically obtained against various TiN and capping layer thicknesses in high-k/metal gate field-effect transistors (FETs). It is known that the magnitude of |dVth/dT| for such FETs is larger than that of polycrystalline silicon (poly-Si) gate FETs. The origins of the dVth/dT difference among high-k/metal gate FETs were attributed to differences in the temperature coefficient of flat band voltage (=dVFB/dT) and the equivalent gate oxide thickness (EOT). Thicker TiN layers reduced dVFB/dT, which enlarged the magnitude of |dVth/dT|. The EOT increased as the TiN metal layer or Al2O3 capping layer increased in thickness. The large EOT led to an increase in |dVth/dT|, since dVth/dT is a function of the inverse of gate capacitance. In contrast, La2O3 capping hardly affected dVth/dT. This is because La2O3 capping did not affect EOT differently from Al2O3 capping. The relationship between dVth/dT and EOT implies that EOT scaling relieves the issue of large |dVth/dT| for high-k/metal gate FETs.

Al2O3/Ga2O3(Gd2O3) passivation on In0.20Ga0.80As/GaAs—structural intactness with high-temperature annealing

Molecular beam epitaxy grown Al2O3/Ga2O3(Gd2O3)/In0.20Ga0.80As/GaAs has been rapidly thermal annealed to 850 °C in N2. The hetero-structure remained intact, with the In0.20Ga0.80As/GaAs interface being free of misfit dislocation and In0.20Ga0.80As strained, as observed by high-resolution transmission electron microscopy and high-resolution x-ray diffraction using synchrotron radiation. Excellent capacitance–voltage characteristics as well as low electrical leakages were obtained. These structural and electrical results demonstrate that employing Ga2O3(Gd2O3) as a dielectric with an in situ Al2O3 capping layer efficiently protects strained InGaAs layers from relaxing and volatilizing during rapid thermal annealing to 850 °C, important for fabricating inversion-channel InGaAs metal–oxide–semiconductor field-effect-transistors, a candidate for beyond the 16 nm node complementary MOS technology.

Work Function and Effective Oxide Thickness Engineering via Alloying of Metal Gate Electrodes

Dielectric capping layer and electrode alloying approaches for tuning the effective work function and effective oxide thickness of metal oxide semiconductor transistors are compared. TaMgC and MoAlN electrodes are compared to MgO and Al2O3 capping layers for n-type and p-type transistors respectively. Results indicate that by incorporating the Mg or Al into the gate electrode instead of into the dielectric capping layer reductions in threshold voltage can be achieved, but with the added benefit of an effective oxide thickness reduction. SIMS results suggest that the threshold voltage shift is likely caused by the inward diffusion of Mg or Al though the gate dielectric towards the bottom interface layer. The limitations of each approach for work function engineering are discussed.