AI Era Research Articles

FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems

A series FinFET based non-volatile logic gates with multiple logic functions defined by embedded non-volatile states are proposed for the first time and demonstrated in advanced CMOS technology platform. The device channels in the proposed CMOS logic gate is controlled by a metal floating gate coupled by slot contacts uniquely available in the FinFET process employed in this study. The new logic gate with non-volatile states only enable reconfiguration ability in a Boolean computing unit at a gate level aimed for adaptive and specialized systems in the AI era. Furthermore, the extended applications in tunable ring oscillators for multi-functional IOT modules are successfully demonstrated in this study.

A Japanese Chess Boy, Fujii, in the AI Era

ちょうど2年前の10月1日にプロ入りした将棋の中学生棋士・藤井聡太4段は今年4月，名古屋大学附属高校1年に進級し，5月には早くも7段に昇格した。この2年間の快進撃ぶりは一般ニュースでも逐一報じ

4차 산업혁명 AI시대 인성교육의 방법과 전망

4차 산업혁명 AI시대 인성교육의 방법과 전망

GXNOR-Net: Training deep neural networks with ternary weights and activations without full-precision memory under a unified discretization framework

Although deep neural networks (DNNs) are being a revolutionary power to open up the AI era, the notoriously huge hardware overhead has challenged their applications. Recently, several binary and ternary networks, in which the costly multiply-accumulate operations can be replaced by accumulations or even binary logic operations, make the on-chip training of DNNs quite promising. Therefore there is a pressing need to build an architecture that could subsume these networks under a unified framework that achieves both higher performance and less overhead. To this end, two fundamental issues are yet to be addressed. The first one is how to implement the back propagation when neuronal activations are discrete. The second one is how to remove the full-precision hidden weights in the training phase to break the bottlenecks of memory/computation consumption. To address the first issue, we present a multi-step neuronal activation discretization method and a derivative approximation technique that enable the implementing the back propagation algorithm on discrete DNNs. While for the second issue, we propose a discrete state transition (DST) methodology to constrain the weights in a discrete space without saving the hidden weights. Through this way, we build a unified framework that subsumes the binary or ternary networks as its special cases, and under which a heuristic algorithm is provided at the website https://github.com/AcrossV/Gated-XNOR. More particularly, we find that when both the weights and activations become ternary values, the DNNs can be reduced to sparse binary networks, termed as gated XNOR networks (GXNOR-Nets) since only the event of non-zero weight and non-zero activation enables the control gate to start the XNOR logic operations in the original binary networks. This promises the event-driven hardware design for efficient mobile intelligence. We achieve advanced performance compared with state-of-the-art algorithms. Furthermore, the computational sparsity and the number of states in the discrete space can be flexibly modified to make it suitable for various hardware platforms.

What Is Necessary for Radiation Technology Studies for Big Data and AI Era?

What Is Necessary for Radiation Technology Studies for Big Data and AI Era?