Advanced SOI MOSFETs Research Articles

Mobility model for advanced SOI-MOSFETs including back-gate contribution

In this report it is verified that advanced SOI-MOSFETs with very thin silicon-on-insulator (SOI) and buried oxide (BOX) layers require an improved mobility modeling which considers the contributions of the back-gate field. Furthermore, a newly developed compact mobility model is presented, which satisfies these advanced SOI-MOSFET needs and still preserves the universality of the low-field mobility. The important novel modeling property is that the effective electric field is not only determined by the field induced at the surface but is modified by the potential distribution across SOI and BOX layers. With the developed model accurate reproduction of measured current characteristics under a wide variety of bias conditions becomes possible.

On the gm/ID-based approaches for threshold voltage extraction in advanced MOSFETs and their application to ultra-thin body SOI MOSFETs

In this paper, we investigate the transconductance-to-current ratio (gm/ID) methods for the threshold voltage extraction using two popular threshold voltage criteria applicable to advanced bulk and SOI MOSFETs, namely: the condition of the maximum of the second derivative of the inversion charge and of the equality of the drift and diffusion drain current components. Using analytical modeling, we derive the first-order electrical parameters matching these two physical conditions and show that in the ideal MOSFET they do not coincide. The first corresponds to the point on the gm/ID versus gate voltage (Vg) curve where d(gm/ID)/dVG exhibits a minimum and where the ratio of gm/ID to its maximum value is equal to 2/3, whereas the second is met at the point where this ratio equals 1/2. The gm/ID methods for the VTH extraction using the above two criteria and their correlation with other methods are discussed. Since our modeling is based on the unified charge control model, its predictions are expected to be valid for both bulk and SOI MOSFETs. Experimental and simulation results for advanced SOI MOSFETs are used to validate modeling derivations and clarify practical applicability and limitations of the gm/ID methods.

Evaluation of Interface Trap Density in Advanced SOI MOSFETs

The density of traps at the top interface is difficult to assess in advanced SOI MOSFETs with high-K dielectric and ultrathin film. Searching for a characterization strategy, we compare various approaches: front-channel subthreshold slope, back-channel slope, and coupling coefficient between the front and back channels. The back-channel slope shows the largest variation with the front trap density. However, the resolution may not be sufficient for MOSFETs with very thin buried oxide.

Mobility enhancement by CESL strain in short-channel ultrathin SOI MOSFETs

The electrical properties of front and back channels in advanced SOI MOSFETs (ultrathin film, short length, metal-gate/high-K stack, thin BOX) are used to reveal the impact of tensile and compressive CESL strain. The benefit of compressive strain is maximized in 100nm long MOSFETs, where the hole mobility can be increased by a factor of two. In shorter devices, the mobility gain fades away due to neutral defects and remote Coulomb scattering. The short-channel scattering and strain mechanisms are identified by low temperature measurements and explained by an original physics-based model.

In Situ Comparison of Si/High- $\kappa$ and $\hbox{Si}/ \hbox{SiO}_{2}$ Channel Properties in SOI MOSFETs

Detailed measurements of front- and back-channel characteristics in advanced SOI MOSFETs (ultrathin Si film, high-kappa, metal gate, and selective epitaxy of source/drain) are used to reveal and compare the transport properties at the corresponding Si/high- kappa (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> or HfSiON) and Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility, threshold voltage, and subthreshold swing. As compared with Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , the low-field mobility is lower at the Si/high-kappa interface and increases less rapidly at low temperature, reflecting additional scattering mechanisms governed by high-kappa and neutral defects.

Noise Behavior of a 180 nm CMOS SOI Technology for Detector Front-End Electronics

This paper is motivated by the growing interest of the detector and readout electronics community towards silicon-on-insulator CMOS processes. Advanced SOI MOSFETs feature peculiar electrical characteristics impacting their performance with respect to bulk CMOS devices. Here we mainly focus on the study of these effects on the noise parameters of the transistors, using experimental data relevant to 180 nm fully depleted SOI devices as a reference. The comparison in terms of white and 1/f noise components with bulk MOSFETs with the same minimum feature size gives a basis of estimate for the signal-to-noise ratio achievable in detector front-end integrated circuits designed in an SOI technology.

Transition from partial to full depletion in advanced SOI MOSFETs: Impact of channel length and temperature

This paper presents a detailed investigation of short-channel effects in advanced partially depleted SOI NMOSFETs. The influence of the back-gate voltage on the threshold voltage reveals the increase of the coupling effect with the channel length. The channel length impact is reversed by using pocket implants. Then SOI devices from the same wafer can behave as fully or partially depleted according to the channel length. This effective doping mechanism is amplified at low temperature operation. Systematic measurements show that long channel transistors become fully depleted before short channels, in particular when decreasing the temperature. The reduction of the channel length or the increase of the back-gate voltage and temperature attenuate the gate-induced floating body effect.

Short-channel, Narrow and Ultra-Thin Oxide Effects in Advanced SOI MOSFETS

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Integration of buried insulators with high thermal conductivity in SOI MOSFETs: Thermal properties and short channel effects

SOI circuits exhibit excellent performance and scalability but suffer from self-heating. Systematical 2D simulations demonstrate that the thermal dissipation in SOI MOSFETs can be improved dramatically by replacing the buried oxide with high thermal conductance insulators. The self-heating can be reduced by as much as 50–100 °C. Yet, these materials feature high- K dielectric constant, which also affects the electrical properties: more severe short-channel effects, parasitic capacitances and drain-to-body fringing fields. The conciliation between the thermal and electrical properties of advanced SOI MOSFETs (50 nm long, 10 nm thick) is examined by comparing different SOI materials (air, SiO 2, diamond, AlN, Al 2O 3, SiC) and MOS architectures. We demonstrate the advantage of a ground plane (GP) located under the buried insulator (BOX). Diamond is excellent candidate for relatively thick BOX whereas Al 2O 3 and SiC are suitable for ultra-thin BOX. These novel structures can be fabricated by wafer bonding technology.

Low frequency noise and hot-carrier reliability in advanced SOI MOSFETs

The scaling of the front gate oxide thickness in SOI devices has resulted in gate-induced Floating Body effect observed for the first time in 0.13μm SOI CMOS technologies with ultra-thin gate oxide (sub-2 nm). We give an overview of this new kind of Floating Body effect. Moreover, with SOI to be adapted as a mainstream technology in the forthcoming years, two issues are still of a critical interest regarding circuit applications: low frequency noise behavior and hot-carrier reliability in state-of-the-art SOI MOSFETs. Both are thoroughly investigated in advanced SOI devices in this paper.

Advanced SOI MOSFETs with buried alumina and ground plane: self-heating and short-channel effects

SOI circuits exhibit excellent performance and scalability but suffer from self-heating. This critical problem is systematically analyzed by using an equivalent thermal circuit and 2-D simulations. We demonstrate that the thermal dissipation and self-heating in SOI MOSFETs can dramatically be improved by modifying the generic SOI structure: replacement of the buried oxide with buried alumina. However, alumina is a high- K dielectric which also affects the electrical properties: the drain-to-substrate fringing fields are enhanced, leading to more severe short-channel effects. The trade-off between the thermal and electrical performance of very advanced SOI transistors (10–100 nm long, 5–100 nm thick) is examined by comparing various SOI materials and MOS architectures. The optimum solution consists of a ground plane located underneath a relatively thin buried alumina.

Novel SOI p-channel MOSFETs with higher strain in si channel using double SiGe heterostructures

We have studied p-channel advanced SOI MOSFETs using double SiGe heterostructures fabricated by the combination of SIMOX and high-quality strained-Si/SiGe regrowth technologies, in order to introduce higher strain in Si channel. It was revealed that this double SiGe structure of second Si/sub 0.82/Ge/sub 0.18/Si/sub 0.93/Ge/sub 0.07/allows the second SiGe layer to relax by about 70%, because of the elastic energy balance between the second and the first-SiGe layers. As a result, the strain of Si layer on this double SiGe structure becomes higher than that of the single SiGe structure. Strained SOI p-MOSFETs using the double layer SiGe structure exhibited higher hole mobility than that of strained-SOI MOSFETs with single Si/sub 0.9/Ge/sub 0.1/ structure. The hole mobility enhancement of 30% and 45% was achieved in the strained-SOI MOSFETs with double SiGe structures, compared to that of the universal curve and the control-SOI MOSFETs, respectively.