Advanced RISC Machines Research Articles

Lockstep Dual-Core ARM A9: Implementation and Resilience Analysis Under Heavy Ion-Induced Soft Errors

This paper presents a dual-core lockstep (DCLS) implementation to protect hard-core processors against radiation-induced soft errors. The proposed DCLS is applied to an Advanced RISC Machine Cortex-A9 embedded processor. Different software optimizations were evaluated to assess their impact on performance and fault tolerance. Heavy ions’ experiments and fault injection emulation were performed to analyze the system susceptibility to errors and the DCLS performance. Results show that the approach is able to decrease the system cross section and achieve high protection against errors. The DCLS successfully protects the system from up to 78% of the injected faults. The execution performance analysis shows that by reducing the number of verifications and augmenting the block partition execution time, it is possible to increase the system reliability with minimal performance losses.

Robot vision ultra-wideband wireless sensor in non-cooperative industrial environments

In this article, the ultra-wideband technology for localization and tracking of the robot gripper (behind the obstacles) in industrial environments is presented. We explore the possibilities of ultra-wideband radar sensor network employing the centralized data fusion method that can significantly improve tracking capabilities in a complex environment. In this article, we present ultra-wideband radar sensor network hardware demonstrator that uses a new wireless ultra-wideband sensor with an embedded controller to detect and track online or off-line movement of the robot gripper. This sensor uses M-sequence ultra-wideband radars front-end and low-cost powerful processors on a system on chip with the advanced RISC machines (ARM) architecture as a main signal processing block. The ARM-based single board computer ODROID-XU4 platform used in our ultra-wideband sensor can provide processing power for the preprocessing of received raw radar signals, algorithms for detection and estimation of target’s coordinates, and finally, compression of data sent to the data fusion center. Data streams of compressed target coordinates are sent from each sensor node to the data fusion center in the central node using standard the wireless local area network (WLAN) interface that is the feature of the ODROID-XU4 platform. The article contains experimental results from measurements where sensors and antennas are located behind the wall or opaque material. Experimental testing confirmed capability of real-time performance of developed ultra-wideband radar sensor network hardware and acceptable precision of software. The introduced modular architecture of ultra-wideband radar sensor network can be used for fast development and testing of new real-time localization and tracking applications in industrial environments.

Implementation of new hybrid lightweight cryptosystem

Embedded systems, Internet of Things (IoT) and mobile computing devices are used in various domains which include public-private infrastructure, industrial installation and critical environment. Generally, information handled by these devices is private and critical. Therefore, it must be appropriately secured from different attacks and hackers. Lightweight cryptography is an aspiring field which investigates the implementation of cryptographic primitives and algorithms for resource constrained devices. In this paper, a new compact hybrid lightweight encryption technique has been proposed. Proposed technique uses the fastest bit permutation instruction PERMS with S-box of PRESENT block cipher for non-linearity. An arbitrary n-bit permutation is performed using PERMS instruction in less than log (n) number of instructions. This new hybrid system has been analyzed for software performance on Advanced RISC Machine (ARM) and Intel processor whereas Cadens tool is used to analyze the hardware performance. The result of the proposed technique is improved by the factor of eight as compared to the PRESENT-GRP hybrid block cipher. Moreover, PERMS instruction bit permutation properties result a very good avalanche effect and compact implementation in the both hardware and software environment.

The Design and Data-Throughput Performance of Readout Module Based on ZYNQ SoC

ZYNQ has gradually become a flexible and suitable architecture with field-programmable gate arrays and dual-high-performance advanced RISC machine Cortex-A9 processors in applications of data acquisition and readout systems in the field of nuclear electronics. The high data rate and high-efficient data-throughput performance between the programmable logic (PL) and processing system (PS) is essential in a readout module based on ZYNQ. In this paper, four typical readout electronics system architectures are introduced, and the details of hardware and software design of the new-generation compact readout module RAIN1000Z2 based on ZYNQ XC7Z020–CLG400 are illustrated. Then, the data-throughput performance tests between the PL and PS are designed and implemented. The highest performance readout mode can reach more than 2000 MB/s data-throughput in different high-performance port combination modes. In conclusion, recommendation of combination mode is given for different data-throughput applications’ requirements in readout applications based on the ZYNQ-based readout module.

Design and testing of a control system associated with the automatic feeding boat for farming Chinese river crabs

In order to address the issues of nonuniform feeding and high labor cost plaguing the process of farming Chinese river crabs, the present study proposes a multifunctional automatic river crabs feeding boat based on Advanced RISC Machine (ARM) and Global Positioning System / Inertial Navigation System (GPS/INS) integrated navigation. This paper proposes a new calculation method based on real time point insertion. This method calculates the current target position of the boat in the real time according to the position of the boat and the turning points of the current route. A new turning and route-switching strategy is also presented in this paper to improve the ship's operational efficiency and prevent the ship from veering off the target route due to its high speed. Considering the boat's unique movement characteristics including non-linearity, large delay and underdamped nature, a route-speed dual-loop control algorithm is designed based on fuzzy Proportion Integration Differentiation (PID) method. Through analyzing the bait distribution associated with the feeding machine, the present study proposes an inner-spiral-based full coverage traversal method and a travel distance optimization model so as to improve the uniformity of the automatic feeding. Results show that the speed overshoot is no more than 5% and the steady-state error can be kept within 3%. Compared with the finite point method, the real time point insertion method decreases the peak route deviation errors by 82.82% and 84.14% while turning and going straight.

A Fiber Bragg Grating Interrogation System with Self-Adaption Threshold Peak Detection Algorithm.

A Fiber Bragg Grating (FBG) interrogation system with a self-adaption threshold peak detection algorithm is proposed and experimentally demonstrated in this study. This system is composed of a field programmable gate array (FPGA) and advanced RISC machine (ARM) platform, tunable Fabry–Perot (F–P) filter and optical switch. To improve system resolution, the F–P filter was employed. As this filter is non-linear, this causes the shifting of central wavelengths with the deviation compensated by the parts of the circuit. Time-division multiplexing (TDM) of FBG sensors is achieved by an optical switch, with the system able to realize the combination of 256 FBG sensors. The wavelength scanning speed of 800 Hz can be achieved by a FPGA+ARM platform. In addition, a peak detection algorithm based on a self-adaption threshold is designed and the peak recognition rate is 100%. Experiments with different temperatures were conducted to demonstrate the effectiveness of the system. Four FBG sensors were examined in the thermal chamber without stress. When the temperature changed from 0 °C to 100 °C, the degree of linearity between central wavelengths and temperature was about 0.999 with the temperature sensitivity being 10 pm/°C. The static interrogation precision was able to reach 0.5 pm. Through the comparison of different peak detection algorithms and interrogation approaches, the system was verified to have an optimum comprehensive performance in terms of precision, capacity and speed.

Implementation of data path components of ARM7 microprocessor using sub threshold current mode logic with sleep transistor technique

The latest Very Large Scale Integration (VLSI) technology trends have been moving towards making devices cheaper and more powerful for everyone to afford them. So the ultimate focus being reducing power consumption by the gadgets. With the added feature of transistors to be structured in 3D, the Moore’s law is to be continued. Hence, Leakage currents are a major concern with the increasing number of transistors per chip when the technology is scaled, static power dissipation needs to be monitored. Advanced RISC Machine (ARM) Processors have been giving a new definition to smart phones, tablets and other embedded applications. This paper presents a novel technique focusing on low power technology, developing an ARM7 microprocessor using Sleep transistor with Sub threshold Current Mode Logic (STCML) technique in 45nm technology using Cadence Virtuoso Tool. The simulation results have been observed on Spectre simulator and power has been calculated in Analog Design Environment (ADE L).

Comparison of processing speed between Arduino Due and Teensy 3.6 boards in a system identification application

The system identification technique is a powerful real-time signal processing tool when dealing with the characterization of dynamic systems. This approach uses adaptive filtering techniques and the least mean square (LMS) algorithm to estimate the impulse response of a system in a finite impulse response (FIR) filter format. The main purpose of this paper is to compare the results and processing speed of two ARM-based microcontrollers as well as to give a theoretical background and an implementation procedure of the technique. ARM (Advanced RISC Machine) is an architecture of 32-bit processors usually applied in embedded systems due to its processing power, relatively low consumption, cost and small size. The impulse responses obtained by the method for several passive electronic filters were transformed to the frequency domain and compared with simulations of the circuits' frequency responses. This practice was repeated for both boards and for different parameters of the algorithm. The results have shown that the Arduino Due was unable to deal with higher sampling frequencies due to its processor limitations. On the other hand, the Teensy 3.6, a more powerful controller, yields great results even for higher frequencies.

Multi-task parallel collaborative design based on SoC multi-core architecture

The high efficiency is demanded in aerospace field. In the design of the control system, adopting single processor can hardly meet the demand of efficiency required. However processor array's hardware size and off-chip bus delay cannot be ignored. In order to solve the above mentioned problems, this paper is intended to study multi-task collaborative parallel design based on multi-core SOC (system on chip). Firstly, multi-core architecture based on SOC is achieved, which includes constructing two MicroBlaze cores, two ARM (advanced RISC machines) cores and designing inter-core communication, as well as designing external data collection and hardware acceleration unit based on FPGA (field programmable gate array). Secondly, collaborative parallel design in missile control system is studied. Finally, a verification platform is developed. By comparing with single core processor, it is proved that the approaches proposed have advantages over enhancing the efficiency.

Multi-task parallel collaborative design based on SoC multi-core architecture

The high efficiency is demanded in aerospace field. In the design of the control system, adopting single processor can hardly meet the demand of efficiency required. However processor array's hardware size and off-chip bus delay cannot be ignored. In order to solve the above mentioned problems, this paper is intended to study multi-task collaborative parallel design based on multi-core SOC (system on chip). Firstly, multi-core architecture based on SOC is achieved, which includes constructing two MicroBlaze cores, two ARM (advanced RISC machines) cores and designing inter-core communication, as well as designing external data collection and hardware acceleration unit based on FPGA (field programmable gate array). Secondly, collaborative parallel design in missile control system is studied. Finally, a verification platform is developed. By comparing with single core processor, it is proved that the approaches proposed have advantages over enhancing the efficiency.

An Energy-Efficient Programmable Manycore Accelerator for Personalized Biomedical Applications

Wearable personalized health monitoring systems can offer a cost-effective solution for human health care. These systems must constantly monitor patients’ physiological signals and provide highly accurate, and quick processing and delivery of the vast amount of data within a limited power and area footprint. These personalized biomedical applications require sampling and processing multiple streams of physiological signals with a varying number of channels and sampling rates. The processing typically consists of feature extraction, data fusion, and classification stages that require a large number of digital signal processing (DSP) and machine learning (ML) kernels. In response to these requirements, in this paper, a tiny, energy-efficient, and domain-specific manycore accelerator referred to as power-efficient nanoclusters (PENC) is proposed to map and execute the kernels of these applications. Simulation results show that the PENC is able to reduce energy consumption by up to 80% and 25% for DSP and ML kernels, respectively, when optimally parallelized. In addition, we fully implemented three compute-intensive personalized biomedical applications, namely, multichannel seizure detection, multiphysiological stress detection, and standalone tongue drive system (sTDS), to evaluate the proposed manycore performance relative to commodity embedded CPU, graphical processing unit (GPU), and field-programmable gate array (FPGA)-based implementations. For these three case studies, the energy consumption and the performance of the proposed PENC manycore, when acting as an accelerator along with an Intel Atom processor as a host, are compared with the existing commercial off-the-shelf general-purpose, customizable, and programmable embedded platforms, including Intel Atom, Xilinx Artix-7 FPGA, and NVIDIA TK1 advanced RISC machine -A15 and K1 GPU system on a chip. For these applications, the PENC manycore is able to significantly improve throughput and energy efficiency by up to $1872{\times}$ and $276{\times} $ , respectively. For the most computational intensive application of seizure detection, the PENC manycore is able to achieve a throughput of 15.22 giga-operations-per-second (GOPs), which is a $14{\times} $ improvement in throughput over custom FPGA solution. For stress detection, the PENC achieves a throughput of 21.36 GOPs and an energy efficiency of 4.23 GOP/J, which is $14.87{\times} $ and $2.28{\times} $ better over FPGA implementation, respectively. For the sTDS application, the PENC improves a throughput by $5.45{\times} $ and an energy efficiency by $2.37{\times} $ over FPGA implementation.

Design and Implementation of the ZigBee Wireless Sensor Network Based on ARM

This paper is intended to design a ZigBee wireless network node based on the advanced RISC machines (ARM), so as to facilitate the network usage process. The performance of the new sensor is subject to antenna test and simulation experiment. The HFSS simulation method is adopted, and the antenna size and scanning frequency are optimized through analyzing the research status of ZigBee technology and the working principle of ZigBee protocol stack based on parameters, such as, the return loss and direction of the antenna, which not only increases the accuracy of analysis and but also reduces the reflection coefficient. The experimental results show that when L2 is 14. 9mm, the effect is the best, and Sll is -26.6 dB. Based on the above findings, it is concluded that the integrated antennas on the printed circuit board (PCB) board can reduce the production cost of the antennas; thus, IFA antennas can meet the requirements of ZigBee based wireless sensor network in term of antenna performance.

The implementation of a measurement system for brushless DC motor parameters

ABSTRACTMost of the energy conversion in industrial devices and equipment is completed by the motor. The acquirement of motor parameters becomes very important for designing the motor drives. The aim of this paper is to design and implement a motor measurement system. Through the processing of an Advanced RISC Machines (ARM) microcontroller, the various parameters of motors such as input voltage, input current, input power, motor speed, and motor torque can be obtained. Consequently, the torque constant, load torque, viscous friction, and the inertia of the motor are calculated and achieved. The motor parameters can be commanded and displayed in the designed human interface of a PC via USB communication. The hardware system designed in this system includes an ARM microcontroller, an inverter, a voltage sensor, a current sensor, a torque sensor, and power supply. The software programming is developed under the Visual Studio 2012 environment development platform using the C language. Finally, the prototype of the motor measurement system is completed and verified. The experimental results for the motor parameters and torque/speed characteristic are demonstrated and show the feasibility of the complete designed system.

Design and Test of a GBTX-Based Board for the Upgrade of the ALICE TOF Readout Electronics

In order to cope with the increased luminosity that the European Organization for Nuclear Research large hadron collider accelerator will provide after Long Shutdown 2 (2019- 2020), the a large ion collider experiment (ALICE) Time-Of-Flight (TOF) readout board data readout module is currently being redesigned. As a first step toward the final design, a test board hosting a Microsemi Igloo2 field-programmable gate array (FPGA), the radiation-hard Application-Specified Integrated Circuit (ASIC) gigabit transceiver ASIC (GBTX), and the optical transceiver versatile link transceiver (VTRX) has been designed and extensively tested. The basic idea is to use the GBTX ASIC for performing data transmission, trigger distribution, and clock forwarding toward the front-end electronics. Slow control links are implemented via an on-board advanced risc machine processor Ethernet link and via a 1.25-Gbps optical fiber using the Igloo2 FPGA internal serializer/deserializer. The board is going to work in a moderately hostile environment, having to face a total dose of 0.13 krads in ten years and a flux of 0.26 kHz/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of hadrons with energy above 20 MeV. The test board has extensively been tested with a special attention dedicated to the Igloo2-GBTX-VTRX devices. An upper bound estimation of the optical link bit error rate lower than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-14</sup> is given, together with a measurement of the jitter of the GBTX output clock (around 55.3 ps peak-to-peak value), since this is a very crucial parameter for the TOF detector. The performances obtained by connecting the test board to a computer using the standard ALICE data acquisition board (named C-RORC) are also reported.

Cloud computing and big data: Technologies and applications

Cloud computing and big data: Technologies and applications

On Static Binary Translation of ARM/Thumb Mixed ISA Binaries

Code discovery has been a main challenge for static binary translation, especially when the source instruction set architecture has variable-length instructions, such as the x86 architectures. Due to embedded data such as PC (program counter)-relative data, jump tables, or paddings in the code section, a binary translator may be misled to translate data as instructions. For variable-length instructions, once a piece of data is mis-translated as instructions, decoding subsequent bytes could also go wrong. We are concerned with static binary translation for the very popular Advanced RISC Machine (ARM) architectures. Although ARM is considered a reduced instruction set computer architecture, it does allow the mix of 32-bit (ARM) instructions and 16-bit (Thumb) instructions in the same executables. In addition to different instruction lengths, the ARM and Thumb instructions are located at 4-byte or 2-byte aligned addresses, respectively. Furthermore, because ARM and Thumb instructions share the same encoding space, a 4-byte word could sometimes be decoded as one ARM instruction or two Thumb instructions. The correct decoding of this 4-byte word is actually determined at runtime by the least-significant bit of the program counter. For unstripped binaries, the mapping symbols can be used to identify ARM code regions and Thumb code regions. However, for stripped binaries, such mapping symbols are unavailable. We propose a novel solution to statically translate stripped ARM/Thumb mixed executables. Our solution is implemented in a static binary translator. The binary translator further generates multiple versions of translated code for the code regions whose types cannot be determined with our solution. One of the code versions is selected during runtime. The binary translator also includes a series of analyses that enable the removal of most useless code versions. Based on the experimental results on stripped ARM/Thumb mixed binaries in the SPEC2006 and Embedded Microprocessor Benchmark Consortium (EEMBC) benchmark suites, our static binary translator achieves impressive performance when migrating them to run on x86 machines and the space overhead is no more than 10%.

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study.

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation.

An Embedded Iris Image Acquisition Research

&lt;p&gt;In view of the limitation of traditional identification, it is easy to lose and copy keys, cards or ID cards, and it is easy to forget the password. Here, an embedded application system was designed based on the iris identification technology, the functions of gathering, inputing, and registering the iris information and identification can be realized. The system architecture was designed by using the embedded microprocessor of advanced RISC machines (ARM), which is used as the core. The iris sensor was used to gather the iris information, and the development of software was accomplished with the embedded OS Windows CE. The system can be used on the company entrance guard system, customs security of airport and criminal identification.&lt;/p&gt;

Performance and energy efficiency analysis of HPC physics simulation applications in a cluster of ARM processors

SummaryWe analyze the feasibility and energy efficiency of using an unconventional cluster of low‐power Advanced RISC Machines processors to execute two scientific parallel applications. For this purpose, we have selected two applications that present high computational and communication cost: the Ondes3D that simulates geophysical events, and the all‐pairs N‐Body that simulates astrophysical events. We compare and discuss the impact of different compilation directives and processor frequency and how they interfere in Time‐to‐Solution and Energy‐to‐Solution. Our results demonstrate that by correctly tuning the application at compile time, for the Advanced RISC Machines architecture, we can considerably reduce the execution time and the energy spent by computing simulations. Furthermore, we observe reductions of up to 54.14% in Time‐to‐Solution and gains of up to 53.65% in Energy‐to‐Solution with two cores. Additionally, we consider the impact of two processor frequency governors on these metrics. Results indicate that the powersave governor presents a smaller instantaneous power consumption. However, it spends more time executing tasks, increasing the energy needed to achieve the solution. Finally, we correlate the energy consumption with the execution time in the experimental results using Pareto. These findings suggest that it is possible to explore low‐powered clusters for high‐performance computing applications by tuning application and hardware configuration to achieve energy efficiency. Copyright © 2016 John Wiley &amp; Sons, Ltd.

FINGER TOUCH BASED ECG MONITORING

Since few years, study discloses that the evaluation of Electrocardiography (ECG) signals offers important advantage for biometric field. Many heart attacks can be judged and prevented by ECG waveform analysis. In health care centers, there is increase in the number of biomedical equipment used at hospital and home, but those lack in ability to provide handheld ECG monitor. In this paper, finger based ECG monitor system has been adopted. Instead of six electrodes, only two electrodes attached to fingers can give useful ECG waveform.ECG waveform can be displayed on thin film transistor i.e. TFT and personal computer i.e. PC. Advanced RISC machine, Instrumentation amplifier, ECG electrode and ECG signal conditioning, thin film transistor (TFT),ARDUINO board are included in hardware design. ARM ADC programming, TFT and ARDUINO programming and MATLAB programming for PC interfacing have been implemented in software design. Patient can touch the electrodes through fingers and his/her ECG will be displayed on TFT .Same ECG signal can be transferred to PC via USB cable. Investigational outcomes revealed that such a handheld ECG machine is appropriate in results, easy to use, and light weight.