Advanced RISC Machines Research Articles

Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability

An essential consideration in processor design is ensuring reliability, particularly in demanding environments such as outer space and nuclear plants. To mitigate the effects of errors and enable error recovery, processors need to incorporate fault tolerance techniques. One common type of error is SEU (Single Event Upset), which affects various microelectronic devices including microprocessors, microcontrollers, and semiconductor memory devices. While error mitigation techniques have been developed for processors based on architectures like ARM (Advanced RISC Machine) and MIPS (Million Instructions Per Second), there is a gap in research for open-source ISAs (Instruction Set Architecture) like RISC-V, which this paper aims to address. This paper focuses on designing a fault-tolerant microarchitecture for a RISC-V processor that can correct one-bit errors, detect up to two-bit errors, and integrate lockstep and pipeline rollback features at a lower LUTs (Look Up Tables) consumption by re-using the same hardware pipeline for error mitigation and recovery through instruction mimicking. By incorporating these features, the proposed approach enhances the system’s fault tolerance by detecting and correcting errors caused by transient events and achieves a lower effective die size upon realization compared to contemporary works. The proposed microarchitecture design was simulated and synthesized using the Vivado Design Suite 2023.1 and implemented on a Zynq 7000 SoC ZC702 Evaluation Kit.

Field-Programmable Gate Array Architecture for the Discrete Orthonormal Stockwell Transform (DOST) Hardware Implementation

Time–frequency analysis is critical in studying linear and non-linear signals that exhibit variations across both time and frequency domains. Such analysis not only facilitates the identification of transient events and extraction of key features but also aids in displaying signal properties and pattern recognition. Recently, the Discrete Orthonormal Stockwell Transform (DOST) has become increasingly utilized in many specialized signal processing tasks. Given its growing importance, this work proposes a reconfigurable field-programmable gate array (FPGA) architecture designed to efficiently implement the DOST algorithm on cost-effective FPGA chips. An accompanying MATLAB app enables the automatic configuration of the DOST method for varying sizes (64, 128, 256, 512, and 1024 points). For the implementation, a Cyclone V series FPGA device from Intel Altera, featuring the 5CSEMA5F31C6N chip, is used. To provide a complete hardware solution, the proposed DOST core has been integrated into a hybrid ARM-HPS (Advanced RISC Machine–Hard Processor System) control unit, which allows the control of different peripherals, such as communication protocols and VGA-based displays. Results show that less than 5% of the chip’s resources are occupied, indicating a low-cost architecture that can be easily integrated into other FPGA structures or hardware systems for diverse applications. Moreover, the accuracy of the proposed FPGA-based implementation is underscored by a root mean squared error of 6.0155 × 10−3 when compared with results from floating-point processors, highlighting its accuracy.

CAL: Core-Aware Lock for the big.LITTLE Multicore Architecture

The concept of “all cores are created equal” has been popular for several decades due to its simplicity and effectiveness in CPU (Central Processing Unit) design. The more cores the CPU has, the higher performance the host owns and the higher the power consumption. However, power-saving is also one of the key goals for servers in data centers and embedded devices (e.g., mobile phones). The big.LITTLE multicore architecture, which contains high-performance cores (namely big core) and power-saved cores (namely little core), has been developed by ARM (Advanced RISC Machine) and Intel to trade off performance and power efficiency. Facing the new heterogeneous computing architecture, the traditional lock algorithms, which are designed to run on homogeneous computing architecture, cannot work optimally as usual and drop into the performance issue for the difference between big core and little core. In our preliminary experiment, we observed that, in the big.LITTLE multicore architecture, all these lock algorithms exhibit sub-optimal performance. The FIFO-based (First In First Out) locks experience throughput degradation, while the performance of competition-based locks can be divided into two categories. One of them is big-core-friendly, so their tail latency increases significantly; the other is little-core-friendly. Not only does the tail latency increase, but the throughput is also degraded. Motivated by this observation, we propose a Core-Aware Lock for the big.LITTLE multicore architecture named CAL, which keeps each core having an equal opportunity to access the critical section in the program. The core idea of the CAL is to take the slowdown ratio as the matric to reorder lock requests of these big and little cores. By evaluating benchmarks and a real-world application named LevelDB, CAL is confirmed to achieve fairness goals in heterogeneous computing architecture without sacrificing the performance of the big core. Compared to several traditional lock algorithms, the CAL’s fairness has increased by up to 67%; and Its throughput is 26% higher than FIFO-based locks and 53% higher than competition-based locks, respectively. In addition, the tail latency of CAL is always kept at a low level.

Design and experiment of multidimensional and subnanometer stage driven by spatially distributed piezoelectric ceramics.

Multidimensional microdriving stage is one of the key components to realize precision driving and high-precision positioning. To meet nanometer displacement and positioning in the fields of micro-/nano-machining and precision testing, a new six-degree-of-freedom microdriving stage (6-DOF-MDS) of multilayer spatially distributed piezoelectric ceramic actuators (PZTs) is proposed and designed. The interior of the 6-DOF-MDS is a hollow design. The flexure hinge is used as the transmission mechanism, and the series-parallel hybrid driving of the corresponding PZTs achieves the microtranslation in the X, Y, and Z directions and the microrotation around the three axes of the microdriving stage, forming a microdisplacement mechanism with high rigidity and simple structure, which can realize the microfeed of 6-DOF. The force-displacement theory and lug boss structure optimization of the 6-DOF-MDS are analyzed, while the strength checking and natural frequency of the 6-DOF-MDS are also simulated by the finite element method. In addition, the real-time motion control system of the 6-DOF-MDS is designed based on Advanced RISC Machines. Through a series of verification experiments, the stroke and resolution results of the 6-DOF-MDS are obtained, where the displacements in the X, Y, and Z directions are 20.72, 20.02, and 37.60μm, respectively. The resolution is better than 0.68nm. The rotation angles around X, Y, and Z are 38.96″, 33.80″, and 27.87″, respectively, with an angular resolution of 0.063″. Relevant coupling experiments were also performed in this paper; in the full stroke linear running of X-axis, the maximum coupling displacements of the Y- and Z-axes are 1.04 and 0.17μm, respectively, with the corresponding coupling rates of ∼5.0% and 0.8%. The maximum coupling angles for the X-, Y-, and Z-axes are 0.33″, 0.14″, and 2.30″, respectively. Considering the coupling of the 6-DOF-MDS, decoupling measures and specific mathematical models have also been proposed. The proposed multidimensional microdriving stage achieves subnanometer resolution and can be used for the precise positioning and attitude control of precision instruments at the nano-/subnanometer level.

Custom Network Quantization Method for Lightweight CNN Acceleration on FPGAs

The low-bit quantization can effectively reduce the deep neural network storage as well as the computation costs. Existing quantization methods have yielded unsatisfactory results when being applied to lightweight networks. Additionally, following network quantization, the differences in data types between the operators can cause issues when deploying networks on Field Programmable Gate Arrays (FPGAs). Moreover, some operators cannot be accelerated heterogeneously on FPGAs, resulting in frequent switching between the Advanced RISC Machine (ARM) and FPGA environments for computation tasks. To address these problems, this paper proposes a custom network quantization approach. Firstly, an improved PArameterized Clipping Activation (PACT) method is employed during the quantization aware training to restrict the value range of neural network parameters and reduce the loss of precision arising from quantization. Secondly, the Consecutive Execution Of Convolution Operators (CEOCO) strategy is utilized to mitigate the resource consumption caused by the frequent environment switching. The proposed approach is validated on Xilinx Zynq Ultrascale+MPSoC 3EG and Virtex UltraScale+XCVU13P platforms. The MobileNetv1, MobileNetv3, PPLCNet, and PPLCNetv2 networks were utilized as testbeds for the validation. Moreover, experimental results are on the miniImageNet, CIFAR-10, and OxFord 102 Flowers public datasets. In comparison to the original model, the proposed optimization methods result in an average decrease of 1.2% in accuracy. Compared to conventional quantization method, the accuracy remains almost unchanged, while the frames per second (FPS) on FPGAs improves by an average of 2.1 times.

On certain aspects of standardization and operating conditions of automated systems

Objective. In this paper, the main aspects of the operating conditions of the AS are considered, as well as the issues of standardization of the stages of the life cycle of the AS (creation, commissioning, maintenance, etc.) at the state level. In this subject area, the technological features of building an AS based on various technical architectures are briefly considered, since both foreign processors based on x86-64 architectures and processors of domestic development based on the Advanced RISC Machine architecture are currently applicable. The use of various components of the AS requires additional study in terms of ordering the composition and configuration of specific SPI. Since each processor has a multi-level architecture, this fact objectively complicates the possibilities for full security testing and detection of all vulnerabilities. Method. In the course of the work, the threats and vulnerabilities of individual components of the AS from the point of view of intentional and unintentional threats are considered. The information on the main state standards applied to ensure the protection of information in the AS at the present time is summarized. Result. The main features of the operating conditions of the AS are considered and it is determined that the vulnerabilities of the components are due to the imperfection of the procedures for developing and covering testing of hardware and software. It is determined that in order to protect information in the AS, it is necessary to build a multi-level protection system with state accreditation. Conclusion. Proposals are presented for the application of state standardization for the protection of information in the AS, taking into account the current and prospective threat landscape, including taking into account the design features (undeclared capabilities) of the components. Overcoming threats is possible with the creation of a multi-level information protection system with state accreditation.

CNN inference acceleration on limited resources FPGA platforms_epilepsy detection case study

<span lang="EN-US">The use of a convolutional neural network (CNN) to analyze and classify electroencephalogram (EEG) signals has recently attracted the interest of researchers to identify epileptic seizures. This success has come with an enormous increase in the computational complexity and memory requirements of CNNs. For the sake of boosting the performance of CNN inference, several hardware accelerators have been proposed. The high performance and flexibility of the field programmable gate array (FPGA) make it an efficient accelerator for CNNs. Nevertheless, for resource-limited platforms, the deployment of CNN models poses significant challenges. For an ease of CNN implementation on such platforms, several tools and frameworks have been made available by the research community along with different optimization techniques. In this paper, we proposed an FPGA implementation for an automatic seizure detection approach using two CNN models, namely VGG-16 and ResNet-50. To reduce the model size and computation cost, we exploited two optimization approaches: pruning and quantization. Furthermore, we presented the results and discussed the advantages and limitations of two implementation alternatives for the inference acceleration of quantized CNNs on Zynq-7000: an advanced RISC machine (ARM) software implementation-based ARM, NN, software development kit (SDK) and a software/hardware implementation-based deep learning processor unit (DPU) accelerator and DNNDK toolkit.</span>

Experimental Investigation on Electromagnetic Immunity and Conduction Immunity of Digital Control Circuit Based on ARM

This paper analyzes the typical functions of digital control circuit and its function modules, and develops a set of digital control circuit equipment based on Advanced RISC Machines (ARM) with typical function modules, including principle design, interference injection trace design, function design, and study the failure mode and threshold of typical function modules. Based on continuous wave (CW) and pulse wave, the direct power injection (DPI) method is used to test the conduction immunity of the digital control circuit, and the failure mode and sensitivity threshold of the digital control circuit are quantitatively obtained. This method can provide experimental verification for the immunity ability of the digital control circuit to different electromagnetic interference.

Real-time laser spot detection and tracking system based on parallel multi-target detection and determination algorithm.

Laser spot detection and tracking play a critical role in laser techniques. However, traditional detection and tracking systems tend to be bulky and lack portability. Therefore, there is a growing emphasis on developing high-performance and miniaturized systems based on the field programmable gate array (FPGA). In this paper, a novel parallel multi-target detection and determination algorithm is proposed to address the issue of current FPGA-based systems' ineffective detection of laser spots in complex environments. Our simulation results demonstrate that the algorithm can effectively detect laser spots in complex environments. It can process a frame with an 800 × 480 resolution in only 7.88ms at a 50MHz image processing frequency, which means it can process more than 100 f/s and meet the real-time detection requirements. Such excellent detection performance is challenging to achieve with central processing units and advanced RISC machine microprocessors. Then, the algorithm is further deployed on an FPGA to build a prototype laser spot detection and tracking system. Practical tests show that the system can achieve a spot detection accuracy of around 90% under different luminous intensities, indicating excellent robustness of the designed algorithm. Besides, with the use of a piezoelectric actuator, speedy and precise tracking of the laser spot is implemented. The characteristics of speedy response, self-latching in power off, and no electromagnetic interference of the piezoelectric actuator give the system tremendous advantages in developing high-precision wireless communication control technology, which further broadens the application of the proposed system.

Attention-Enhanced Lightweight One-Stage Detection Algorithm for Small Objects

The majority of object detection algorithms based on convolutional neural network are focused on larger objects. In order to improve the accuracy and efficiency of small object detection, a novel lightweight object detection algorithm with attention enhancement is proposed in this paper. The network part of the proposed algorithm is based on a single-stage framework and takes MobileNetV3-Large as a backbone. The representation of shallower scale features in the scale fusion module is enhanced by introducing an additional injection path from the backbone and a detection head specially responsible for detecting small objects is added. Instead of pooling operators, dilated convolution with hierarchical aggregation is used to reduce the effect of background pixels on the accuracy of small object locations. To improve the efficacy of merging, the spatial and channel weights of scale features are modified adaptively. Last but not least, to improve the representation of small objects in the training datasets, the Consistent Mixed Cropping method is also proposed. The small labels of standard datasets are expanded with the self-collected samples for the training of the algorithm network. According to the test results and visualization on the 64-Bit Extended (X86-64) platform and embedded Advanced RISC Machine (ARM) platform, we find that the average accuracy (mAP) of the proposed algorithm is 4.6% higher than YOLOv4 algorithm, which achieves better small object detection performance than YOLOv4 algorithm, and the computational complexity is only 12% of YOLOv4 algorithm.

Convolutional Neural Network-Based Low-Powered Wearable Smart Device for Gait Abnormality Detection

Gait analysis is a powerful technique that detects and identifies foot disorders and walking irregularities, including pronation, supination, and unstable foot movements. Early detection can help prevent injuries, correct walking posture, and avoid the need for surgery or cortisone injections. Traditional gait analysis methods are expensive and only available in laboratory settings, but new wearable technologies such as AI and IoT-based devices, smart shoes, and insoles have the potential to make gait analysis more accessible, especially for people who cannot easily access specialized facilities. This research proposes a novel approach using IoT, edge computing, and tiny machine learning (TinyML) to predict gait patterns using a microcontroller-based device worn on a shoe. The device uses an inertial measurement unit (IMU) sensor and a TinyML model on an advanced RISC machines (ARM) chip to classify and predict abnormal gait patterns, providing a more accessible, cost-effective, and portable way to conduct gait analysis.

A novel smart photoelectric lock system: Speech transmitted by laser and speech to text

We propose a circuit that modulates a speech signal to a laser, using which the speech signal can be transmitted using the laser. Also, it shows the use of a platform based on embedded ARM (Advanced RISC Machine), running a small deep learning model based on TDNN (Time delay neural network) and LSTM (Long short-term memory), and converting speech to text, and use the text cipher for unlocking. This research implements a smart lock system that can set a pre-record speech cipher and verify the similarity through a laser transmission speech cipher to unlock it. In our experiment result, the English speech of laser transmission can reach a WER (Word error rate) of 14.06% through the deep learning model to recognize the content of the speech cipher. We also design a similarity comparison algorithm based on LCS (Longest common subsequence) to compare the character set of the laser transmission speech compare and the prerecord speech cipher to calculate the similarity rate. Through the similarity comparison algorithm, when the WER is 27.27%, the male speech samples used in this study still have a 95% unlocking success rate, while the female speech samples have a 100% unlocking success rate. Compared with only using automatic speech recognition (ASR) to unlock, the method we propose is to compare the similarity of the content of speech cipher. The method significantly improves the unlocking fault tolerance of using lasers to transmit audio. Therefore, by using the laser to transmit the speech cipher, the usability of the photoelectric smart lock system has been significantly improved. At the same time, the characteristics of the laser are not easy to eavesdrop on the cipher, which can also improve security.

IIoT Deep Malware Threat Hunting: From Adversarial Example Detection to Adversarial Scenario Detection

Protecting widely used deep classifiers against black-box adversarial attacks is a recent research challenge in many security-related areas, including malware classification. This class of attacks relies on optimizing a sequence of highly similar queries to bypass given classifiers. In this article, we leverage this property and propose a history-based method named, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stateful query analysis (SQA)</i> , which analyzes sequences of queries received by a malware classifier to detect black-box adversarial attacks on an industrial Internet of Things (IIoT). In the SQA pipeline, there are two components, namely the similarity encoder and the classifier, both based on convolutional neural networks. Unlike the state-of-the-art methods, which aim to identify individual adversarial examples, tracking the history of queries allows our method to identify adversarial scenarios and abort attacks before their completion. We optimize SQA using different combinations of hyperparameters on an advanced risc machine (ARM)-based IIoT malware dataset, widely adopted for malware threat hunting in industry 4.0. The use of a novel distance metric in calculating the loss function of the similarity encoder results in more disentangled representations and improves the performance of our method. Our evaluations demonstrate the validity of SQA via a detection rate of 93.1% over a wide range of adversarial examples.

Software and hardware co-design and implementation of intelligent optimization algorithms

In order to improve the operating efficiency of the algorithm, some intelligent optimization algorithms are considered to be implemented on hardware. However, the existing design scheme has the problem of poor versatility. Therefore, this paper proposes a general software–hardware co-design scheme of intelligent optimization algorithms. In the design scheme, the initialization module and fitness module of the algorithm are deployed on the Advanced RISC Machines (ARM) for execution to increase the flexibility of the program. The update module of the algorithm is deployed on the Field Programmable Gate Array (FPGA) for execution to realize the hardware acceleration. The data between ARM and FPGA is transferred through Advanced eXtensible Interface (AXI) bus. In this paper, the PSO, BA, WOA, GWO, CMAES and EO algorithms are implemented with the proposed design scheme. And the six algorithms are tested on thirteen benchmark functions of different types. The experimental results prove the feasibility of the design scheme. In addition, by comparing with software and other implementation methods in execution time, resource occupancy and convergence, the effectiveness and superiority of the proposed scheme are proved.

Design and test of portable comprehensive quality non-destructive detector for grape bunches based on spectrum

Based on the analysis technology of visible/near infrared diffuse reflectance spectroscopy a portable and nondestructive detector was designed to test comprehensive quality of red globe grape bunches in growing period. The detector includes spectrum acquisition probe, spectrometer, lithium battery, halogen lamp light source, ARM board and peripheral circuit. Based on MFC development tool, the real-time analysis and processing software of the detector is written by C++ language. The optimal partial least squares regression (PLSR) detection model of multi-quality parameters was implanted into the hardware device. This paper selects the red globe grape bunches in the growth period as the research samples, collects the visible / near-infrared diffuse reflectance spectrum information, and then uses the established PLSR model to detect the Soluble solid content(SSC), Total acid (TA) and pH of the samples to generate comprehensive quality parameters. So as to realize the nondestructive testing of multiple quality and comprehensive quality parameter of red globe grape bunches in the growth period. In conclusion, the detector can realize real-time and non-destructive detecting of red globe grape bunches in growth period aiming at the multiple quality and comprehensive quality. Based on the analysis technology of visible/near infrared diffuse reflectance spectroscopy a portable and nondestructive detector was designed to test comprehensive quality of red globe grape bunches in the growth period. The detector included spectrum acquisition probe, spectrometer, lithium battery, halogen lamp light source, advanced RISC machines (ARM) board and peripheral circuit. Based on microsoft foundation classes (MFC) development tool, the real-time analysis and processing software of the detector was written by C++ language. The optimal partial least squares regression (PLSR) detection model of multi-quality parameters was implanted into the hardware device. This paper selected the red globe grapes bunches in the growth period as the research samples, collected the visible/near infrared diffuse reflectance spectrum information, and then used the established PLSR model to detect the soluble solid content (SSC), total acid (TA) and pH of the samples to generate comprehensive quality parameter. So as to realize the nondestructive detecting of comprehensive quality of red globe grapes bunches in the growth period. In conclusion, the detector could realize real-time and non-destructive detecting of red globe grapes bunches in growth period aiming at the comprehensive quality.

Real-Time 2D-to-3D Conversion for Television Broadcasting Based on Embedded System

In this article, we present an efficient 3-D display technique that employs current 2-D television (TV) channels. First, a gradient background depth is generated for the still region. To create a stereo effect, multiple objects are detected and segmented using the binary format. Object depth is estimated according to the object size and its location. Depth value is assigned as a proportion of the object size using the linear quantitative method. Each object size is calculated and its depth value is proportional to the size parameter. If an object is the largest one and is located in the central region, the maximum depth value is assigned. For real-time implementation, dual advanced RISC machine (ARM) cores perform the task using the algorithm of the proposed stereo conversion. Our results show that a low-cost embedded system can perform the proposed 3-D algorithm, with a processing time of 43 ms per frame. The signal from a TV channel can be sampled and converted to a 3-D format display on a conventional LCD screen.

A New Electro-Optical-Thermal Modelling for Non-Dispersive IR Sensing Technique of Gas Concentration

In this research, a new electro-optical-thermal modeling is proposed and built by simulation program with integrated circuit emphasis (SPICE). In particular, it is constructed for use in the non-dispersive infrared (NDIR) sensing technique of gas concentration. This model, based on the theory of circuitry and the Beer-Lambert law, includes various equivalent elements for the optics, sensor, and circuits. To build and investigate the validity of the proposed model, an NDIR for measurement of CO2 is built with the hybrid combination of a thermopile sensor with a specific wavelength filter, an infrared micro electro mechanical systems (MEMS) heater, an optical tube, amplification circuits with a chopper amplifier, advanced RISC machine (ARM)-based micro processing unit and discrete electronic devices. The thermal properties of the light source with periodic modulation have been studied from the output signal of a thermopile within the limit of modulation frequency. Based on the thorough measurements of output signals and transient responses, the thermal and optical parameters of the sensor and optical components for this model are extracted. The comparison of the simulation and experimental data of the NDIR measurement for different CO2 concentrations shows a great agreement with a maximum error of 0.27% at 3500 ppm. This approach allows for the development of a high-level sensor and circuit integrated simulation based on the most fundamental principles and multiple variables.

Design and Implementation of Low-Cost Distributed Tabletop Magnetic Particle Imaging System

Magnetic particle imaging (MPI) is a novel tomography model that mainly benefits from the nonlinear magnetization response of magnetic nanoparticles under a dramatically changing magnetic field. Low-cost and compact system construction is beneficial to the application of education, biomedical research, preclinical and clinical medicine. Conversely, many aspects of the production cost, infrastructure requirements, and distributed measurements can be prohibitively expensive for them. In this article, a low-cost, compact tabletop MPI scanner based on a field-programmable gate array (FPGA) framework with an Advanced RISC Machine (ARM) cores was proposed to address these issues. First, the proposed low-cost MPI scanner was realized by substituting discrete elements, which is affordable to cover the most economically underdeveloped regions. Besides, the ARM cores embedded in the FPGA framework which has the inherent advantages of low-power operation, are exploited to execute high-power real-time data transmission tasks instead of conventional X86. And a customized tabletop MPI system was constructed via the proposed architecture for advanced distributed MPI research. Simulative vessel experiments with commercial superparamagnetic nanoparticles (SPIONs) have been performed in the proposed system by vessel phantoms. The experimental images showed that the proposed system could achieved an image resolution of approximately 2 mm, which can distinguish spatial locations of brain veins (2–4 mm in diameter). Moreover, the experiment of distributed transmission showed that the proposed system could perform the collection and transmission of distributed particle signals based on the inherent user datagram protocol (UDP) network transmission protocol with an average round trip time (RTT) of 28.044 ms. Hence, the proposed system has the potential to apply the network cloud to get distributed biomedical information for remote education or diagnosis.

Research on State Monitoring System of Intelligent Disconnecting Switch Based on Sensing Technology

The intelligentization, informationization, and internalization of power system infrastructure equipment are the key technologies to achieve the low-carbon transformation of the power system. To tackle the low degree of intelligence and the internet in the monitoring and early warning of mechanical faults of the disconnecting switch, this paper designs an intelligent monitoring system for the disconnecting switch operation status based on sensing technology. Torque sensors, angle encoders, micro-switches, attitude sensors, and temperature and humidity sensor technology are used to monitor the operation status of the disconnecting switch, and an advanced RISC machine (ARM) embedded terminal system is used as the disconnecting switch status monitoring center. The intelligent monitoring system aims to accurately monitor the temperature and humidity environment in the disconnector operating mechanism box, the opening and closing position state of the disconnector, and the torque angle variation characteristics of the disconnector according to the operating parameters collected by the sensor, while achieving remote real-time state monitoring of the disconnecting switch. The function tests and field tests show that the system performance is stable, and the state information collection, intelligent analysis, and remote monitoring meet the actual needs, which can improve the efficiency of disconnecting switch operation, maintenance, and overhaul, thereby reducing the risk of power grid outages.

Design and Application of Smart Vision Sensor Using Embedded Technology in Cost Management of Power Transmission and Transformation Project in Ningxia Companies

The purpose is to solve the problems of cumbersome calculation, low accuracy, poor timeliness, rigid data acquisition, high cost, large volume, and insufficient signal processing capacity of traditional vision sensor (VS) in Ningxia companies. Firstly, this paper designs an embedded smart VS based on advanced RISC machines (ARM) processor. Secondly, it proposes a cost estimation algorithm for power transmission and transformation project (PTTP) based on particle swarm optimization-least squares support vector regression (PSO–LSSVR). Afterward, a cost estimation model of PTTP based on building information modeling (BIM) is proposed. Thirdly, historical cost data of PTTP of a Ningxia company within five years are selected as data samples to verify the accuracy of the PSO-LSSVR estimation algorithm and BIM model. The results show the following: (I) The measurement error of the designed smart VS is less than 4%, with high accuracy, which is suitable for large-scale measurement in the construction site. (II) The error of the PSO-LSSVR algorithm in engineering cost prediction is less than 20%, and the accuracy is higher than that of traditional support vector machine (SVM) and LSSVR algorithms. The optimization effect is remarkable and can be used for the feasibility analysis of PTTPs. (III) The proposed BIM-based PTTP cost estimation model error in the project cost estimation is controlled within 10%. With high accuracy, it can be applied to the PTTP management of Ningxia company. The purpose is to provide important technical support for the upgradation of traditional VS technology and the realization of visual management and rapid cost estimation of PTTP of Ningxia companies.