Advanced Microcontroller Bus Architecture Research Articles

Green Computing: Crafting A Low-Energy Amba APB Bridge Solution

Abstract—The Advanced High-performance Bus (AHB), a key component of the Advanced Microcontroller Bus Architecture (AMBA) family, stands as a high-performance, low-power, and high- bandwidth communication interface within system components. Bridging to low-bandwidth peripherals, the Advanced Peripheral Bus (APB) offers a simple, non-pipelined protocol for read- and-write communication, linking a bridge/master to numerous slaves via a shared bus. The AHB to APB bridge serves a critical role in integrating diverse bus protocols, facilitating efficient communication between high-performance processing units and slower peripherals, thereby enhancing the System-on-Chip (SoC)'s overall effectiveness and functionality. This approach addresses the functional verification of the AMBA AHB to APB Bridge protocol with a focus on completeness. We employ a layered testbench architecture in System Verilog to ensure thorough verification of functionality with maximal coverage. Our verification environment is constructed using System Verilog, and simulations are conducted on the EDA playground platform. Through this comprehensive approach, we aim to provide robust validation of the AHB to APB bridge protocol, ensuring its reliability and compatibility within complex SoC designs. Keywords— Advanced Peripheral Bus (APB), System-On-Chip (SOC), Advanced Microcontroller Bus Architecture.

Adaptive neural acceleration unit based on heterogeneous multicore hardware architecture FPGA and software-defined hardware

ABSTRACT This study is anchored in a heterogeneous multicore hardware architecture, specifically Field Programmable Gate Arrays (FPGAs), and software-defined hardware. It employs dynamic planning for the reconfiguration of a software-defined System-on-Chip (SOC) to expedite neural network processes. The reconfigured software-defined SOC serves as an efficient data processor, facilitating the hybrid development and verification of domain-specific System-on-Chip architectures, adhering to the Advanced Microcontroller Bus Architecture (AMBA) standard. The proposed block data trimming methodology significantly enhances overall hybrid computing efficiency by mitigating throughput limitations inherent in Systolic array hardware. The designed Systolic array Matrix Multiply Unit (MMU) is evaluated for a maximum MMU size of 32 × 32 and 1,024 Multiply Accumulator (MAC) units. Hybrid dynamic circuits are devised for the synthesis of int8, int16, int32, and int64 data types and associated logic circuits to validate the performance of parallel computing. It is anticipated that this proposed system can find utility in the development and deployment of unmanned devices, as well as in the integration of deep learning and multi-sensory fusion involving acoustic, tactile, and force sensory components.

Development of SRAM-APB protocol interface and verification

The purpose of this mechanism is to enhance the chip’s internal connections and read/write memory capabilities. The Advanced Microcontroller Bus Architecture (AMBA) is one such shared bus that uses static random-access memory to achieve this goal. As a result, it’s important to weigh a variety of design options before diving into the Verilog description. It’s also important to remember that the system must be designed to accommodate a large number of interoperable modules and memories. The design, on the other hand, starts with fewer modules and a less complicated description and realisation that relies on memory access. ModelSim is used to simulate after the delay has been modelled in Verilog. Since the interface’s static random-access memory uses an APB protocol, its performance may be tested at this stage. In addition, Questasim employs verification modules and System Verilog technologies to guarantee the system’s operation. From the obtained results, the Direct Memory Access (DMA) with SRAM-APB outperforms the alternatives, particularly in frame transmission schemes, with a wire efficiency that is 1.4 times higher and a dynamic energy efficiency that is nearly twice as high as those of conventional configurations.

Review on Design and Verification of an Advanced Extensible Interface - 4 Slave Devices

An essential part of a system on a chip (SoC) is not just the components or blocks that it contains, but also how these components and blocks are connected to one another. Advanced Microcontroller Bus Architecture (AMBA) is a system that enables the individual blocks to interact with one another. These protocols have established the de facto standard for 32-bit embedded processors because they are widely documented and may be used without the payment of royalties. High-performance and high-frequency system designs may be designed with the aid of the AMBA AXI 4 protocol. It's ideal for systems that need both large bandwidth and low latency since it enables high-frequency operation without the use of complicated bridges. In addition to being compatible with older versions of the AHB and APB interfaces, it also allows for a wide range of possible configurations for the network's interconnects. Without the need for a bridge, many peripherals may be connected into AMBA-based CPUs via the use of this slave interface. By constructing a wrapper over the AXI4 slave interface, the newly created slave interface may also be used to link non-AMBA-based CPUs to a variety of peripherals. These peripherals include SPI, I2C, and UART, amongst others

Design and Synthesis of AMBA APB Protocol for SoC

The AMBA (Advanced Microcontroller Bus Architecture) and APB (Advanced Peripheral Bus) protocol is a widely used bus protocol designed by ARM for integrating peripheral devices into a system-on- chip (SoC) design. It provides a low-power, low-complexity interface that allows efficient communication between the master and slave devices within the SoC. The APB protocol offers a straightforward and flexible architecture, making it suitable for a wide range of SoC applications. It supports a single-master, multiple-slave bus structure, where an APB master can communicate with multiple APB slave devices. This architecture enables seamless integration of various peripheral devices, such as timers, UARTs, I/O controllers, and more, into the SoC. One of the key advantages of the APB protocol is its power efficiency. It achieves this by utilizing a simplified set of signals and reduced complexity compared to other bus protocols. The APB bus operates based on a common clock signal, ensuring proper timing and synchronization of data transfers while minimizing power consumption.

RTL Implementation of AMBA AHB Protocol using Verilog

Abstract: The enactment of a computer system heavily depends on the design of its bus interconnect. A poorly designed system bus can hinder the transmission of instructions and data between the processor and memory or between peripheral devices and memory. To address these challenges, the Advanced Microcontroller Bus Architecture (AMBA) provides an open standard for connecting and managing functional blocks in a System-on-Chip (SoC). This architecture allows for developing multi-processor designs with many controllers and peripherals while ensuring the system is designed correctly the first time. Furthermore, the AMBA specifications are royalty-free and platform-independent. They can be used with any processor architecture. The project will provide an RTL view and an extracted design summary of the AMBA AHB module at the system-on-chip level. The AMBA High-performance Bus (AHB) is another part of the AMBA family of conventions. The AHB is designed to support highperformance, high-clock system modules and serves as the system's high-performance backbone bus. The AHB enables the efficient connection of low-power peripheral functions to processors, on-chip memories, and external off-chip memory interfaces. All signal transitions in the AHB relate only to the rising clock edge, allowing AHB peripherals to be easily integrated into any design flow. The project also describes the AMBA AHB design and implementation using Verilog, with read/write operations implemented using the Xilinx simulator.

Verilog-Based Design of AMBA-APB Protocol and Their Verification

The Advanced Peripheral Bus (APB) is a crucial component of the Advanced Microcontroller Bus Architecture (AMBA), a widely-used standard for designing complex microcontrollers with multiple peripherals. The APB's non-pipelined architecture allows it to connect low-transmission capacity peripherals to the SoC, while minimizing power utilization and interface complexity. The APB is designed to facilitate communication between master and slave devices, supporting multiple slaves in a system. The APB supports three types of transfers: Write, Read, and Idle. The objective of this work is to enable data transfers for Write and Read operations with both No-Wait and Wait states. No-Wait transfers are those that do not require the master to wait for a response from the slave before continuing, while Wait transfers require the master to wait until the slave responds. This allows for efficient and reliable communication between the master and slave devices in the system. To implement this functionality, the Verilog hardware description language (HDL) has been used for design. Verilog offers reusability of Test bench components, allowing for efficient verification of numerous test cases and ensuring the robustness and accuracy of the proposed system. The proposed design and verification methodology with Verilog HDL and a Test bench can thoroughly validate the APB protocol's functionality and performance. This approach enables comprehensive testing of Write and Read operations with No-Wait and Wait states, ensuring that the data transfers occur accurately and efficiently. By utilizing proper simulation and verification using Verilog and a Test bench, the proposed system can be confidently implemented in real-world applications. It provides reliable communication between master and slave devices in a system while minimizing power utilization and interface complexity. The design's reusability enhances the flexibility and adaptability of the system, ensuring that it can be adapted to different applications and scenarios. Overall, the proposed system provides a robust and efficient solution for communication between master and slave devices in an AMBA-based device.

Design and Implementation of IIC Interface IP Core

With the development of SOC (System on Chip) design technology, IPcore reuse technology and on-chip bus technology, which are the basis of SOC design technology, have attracted wide attention from the society. IP core reuse technology can save repetitive work and greatly speed up chip development. At present, China's large-scale SOC design uses more foreign IP cores, which are expensive. IIC(Inter-integrated Circuit) interface is an important peripheral interface in AMBA (Advanced Microcontroller Bus Architecture) bus. It is used for communication between CPU and peripheral devices, and can be used in embedded, radio frequency communication and other fields. Therefore, designing an IIC interface IP has great use value.

CoVerPlan: A Co mprehensive Ver ification Plan ning Framework Leveraging PSS Specifications

With increasing design complexity, the portability of tests across different designs and platforms becomes a key criterion for accelerating verification closure. The Portable Test and Stimulus Standard (PSS) is an emerging industry standard prepared by Accellera for system-on-chip verification and testing. It provides language constructs to create a target-agnostic representation of stimulus and test scenarios reused by various users across many levels of integration. In this article, we present CoVerPlan , a comprehensive verification framework built to explore the power of action inferencing on test models written in PSS. The proposed verification framework leverages a Boolean satisfiability problem planner to unwind the actual verification flow from the PSS specifications and automatically synthesizes target-specific constraint-random testbenches and formal assertions. CoVerPlan also carries out assertion-based verification of the synthesized properties. We demonstrate the efficacy of our proposed framework over several case studies, like the Advanced Microcontroller Bus Architecture advanced peripheral bus protocol, a simple Reduced Instruction Set Computer processor, and a cache coherence protocol.

A Review on Design Implementation and Verification of AMBA AXI- 4 lite Protocol for SoC Integration

Abstract: The present modern bus protocols used for communication between different functional blocks on a System-on-Chip (Soc) designs face many different challenges among which complexity and communication management are the most important factors. These on-chip communications directly impact performance and functionality, hence depending on the application where the bus protocol is to be used, a perfect communication protocol is chosen. AMBA (Advanced Microcontroller Bus Architecture) provides various types of protocols to be used as IP, of which AXI4 (Advance Extensible Interface), is one of the widely used protocols for SoC designs. Out of its three different interconnect protocols: lite, stream and burst, AXI4-lite has the simplest architecture design that best suits to be used in applications where power, area and performance play a vital role. This paper briefs about using AMBA AXI4-lite bus protocol with more bus efficiency and performance in an SoC design for proper communication between various functional blocks present. The RTL is verified using UVM (Universal Verification Methodology) and various designing process is carried out using cadence tools.

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

We propose a network-on-chip (NoC)-based whole system design, whose communication architecture is compatible with the advanced microcontroller bus architecture advanced extensible interface 4 (AXI4) protocol and supports high-performance multiple quality-of-service (QoS) schemes. In our system, the network interface (NI) between the NoC and the master/slave node is proposed to make the NoC architecture independent from the AXI4 protocol via message format conversion between the AXI4 signal format and the packet format, offering high flexibility to the NoC design. Besides, a QoS inheritance mechanism is applied in the slave-side NI to support QoS during packets’ round-trip transfer in the NoC. The NoC system contains time-division multiplexing (TDM) and virtual channel (VC) subnetworks to apply multiple QoS schemes to AXI4 signals with different QoS tags, and the NI is responsible for signals distribution between two subnetworks. Besides, a traffic converter is proposed in each NI to balance the traffic between the two subnetworks when necessary. The experimental results show that our proposed architecture ensures a high-throughput and low-latency NoC system. By applying the traffic converter, the packet latency can be improved.

Design and verification of an ARM Watchdog Timer using UVM

The watchdog timer is an advanced microcontroller bus architecture (AMBA) compliant system-on-chip peripheral. It is an AMBA slave module and connects to the advanced peripheral bus (APB). It consists of a 32-bit down counter with a programmable timeout interval that generates an interrupt and applies a reset to the processor on time out. Verification intellectual property (IP) is a smart way to verify the functional correctness of any complex design. This is achieved by constrained random verification (CRV), which generates legal test scenarios randomly that weed out the bugs and corner cases, thereby validating the characteristic features of the watchdog timer. CRV also builds automated checkers and provides higher coverage goals. In this work, an ARM Watchdog Timer is designed in Verilog and system-on-chip level verification of the same is performed using the universal verification methodology (UVM) by combining both CRV and coverage driven verification (CDV) to ensure its functional correctness.

Designing SPI to I2C Protocol Converter Base on ASIC Technology and Implementing on the FPGA Platform

Nowadays embedded systems are using a lot of different communication standards to transfer data such as USB, UART, SPI, I2C, etc. To be able to transfer data with each communication standard, the system needs at least one controller block for that communication standard. This has added to the complexity of the system and the cost of manufacturing hardware. Embedded systems only support SPI communication if desired, which can still be communicated with peripherals with I2C standard. However, the SPI cannot be directly connected to the I2C but must use a standard communication converter. This paper will primarily focus on designing an IP core communication standard converter from SPI to I2C using APB (Advanced Peripheral Bus) communication as one of the AMBA (Advanced Microcontroller Bus Architecture) communication sets. In particular, APB is a bus used to communicate with peripherals that do not require fast processing speeds such as UART, SPI, I2C, etc.

Development of Flexible Verification Environment for AMBA APB

The SoC (System on Chip) uses AMBA (Advanced Microcontroller Bus Architecture) as an on chip bus. APB (Advanced Peripheral Bus) is one of the components of the AMBA bus architecture. APB is low bandwidth and low performance bus used to connect the peripherals like UART, Keypad, Timer and other peripheral devices to the bus architecture. This paper introduces the AMBA APB bus architecture design. The design is created using the verilog HDL and is tested by a System verilog test- bench. This design is verified using SV. A reuse based methodology for SoC design has become essential in order to meet these challenges. The work embodied in this paper presents the design of APB Protocol and the Verification of slave APB Protocol. Coverage analysis is a vital part of the verification process; it gives idea that to what degree the source code of the DUT has been tested. The functional coverage analysis increases the verification efficiency enabling the verification engineer to isolate the areas of untested function. The design and verification IP is built by developing verification components using Verilog and System Verilog respectfully with relevant tools such as Questasim and Cadence, which provides the suitable building blocks to design the test environment.

Design And Implementation Of Amba Apb Protocol

The APB (Advanced peripheral bus) protocol is a part of AMBA(advanced microcontroller bus architecture) family. Design under test (DUT) is tested and it establishes the communication between master (test bench) and slave (design). It is designed based on a reusable based methodology for system on chip (SOC) which is essential in order to meet the current VLSI challenges. APB involves low bandwidth, low cost and minimal power consumption and is used to connect the Timer, Keypad and other devices to the bus architecture. The work involved is of APB protocol design and implementation. Here we are designing six test cases namely single and multiple write transaction with and without wait, multiple write transaction with and without wait states, multiple read and write transaction with and without wait. The design is programmed using Verilog HDL and tested using verilog test bench. And finally the APB design is verified using QuestaSim tool.

Efficient Support of AXI4 Transaction Ordering Requirements in Many-Core Architecture

The Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface 4 (AXI4) protocol was initially a bus oriented interface designed for on-chip communication. To offer the possibility of utilizing the AXI4 based processors and peripherals in the on-chip network based system, we propose a whole system architecture solution to make the AXI4 protocol compatible with the Network-on-Chip (NoC) based communication interconnect in the many-core architecture. Due to the out-of-order transaction in the NoC interconnect, which conflicts with the ordering requirements specified by the AXI4 protocol, we especially focus on the design of the transaction ordering units, realizing a high-performance and low cost (area) solution to the ordering requirements by the sequence ID (seq_ID) reuse mechanism and a simple but smart seq_ID synchronization process. Besides, the micro-architectures and the functionalities of the transaction ordering units are described and explained in detail for ease of implementation. The experimental results in a C++ based system simulator show that, compared with the state-of-the-art works, our solution can maximally increase the system throughput by 66.0% and decrease the transaction queueing delay in the master-side ordering unit by 91.2%.

Modified Encryption Standard with High Performance through Secure Protocol

The Advanced Encryption Standard (AES) has been accepted worldwide as a desirable algorithm to encryption and decryption sensitive information. In cryptography the unencrypted information referrers to as plaintext it is encrypted into cipher-text, which will in turn be decrypted back into the usable plaintext. The encryption and decryption are based on the type of cryptography system and secret keys. The secret key is responsible for preparing the input key to be used by the cipher in each round. AES with one-stage pipeline producing minor reduction of delay but does not show any improvement in area and power consumption. To overcome the above drawbacks, the basic architecture of AES, which includes encryption and decryption can be modified with one stage pipeline architecture by using one- dimensional Substitute Box (SBOX). Advanced Microcontroller Bus Architecture (AMBA) describes level of an on-chip communication standards for elevated performance embedded microcontrollers. AMBA AHB (Advanced High Performance Bus) is intended for elevated performance and high-frequency clocks. AHB has unique characteristics such as burst transfer, split transaction and single-cycle master bus transfer. 128 bit plain text is guided by AMBA-AHB requirements and can be used to send a plain text block to the cypher per clock cycle.. Plain text of 128 bit is driven by AMBA-Advanced High-performance Bus. AMBA-AHB specifications and supports the transmission to the cipher of a plain text block per clock cycle i.e., Modified Encryption Standard will be implemented with AMBA –AHB driven by input, which provides on-chip communication, increasing security of encryption standard. Propositioning methodology, Modified Encryption Standard will be simulated and synthesized by using Xilinx ISim 14.7 FPGA.

A review on bus protocols and conversion/translator between different protocols

A computer consists of different components/modules and different communication protocols are used among them. These protocols are needed to achieve the interoperability between two devices/modules. Different protocols cannot communicate directly, there is a need for conversion. A protocol converters block is needed. These compact protocol converters create low power, low voltage connection as well as smaller chip area, making it easy to add multiple devices or components. This paper give a brief description of some commonly used bus protocols such as Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), Advanced Microcontroller Bus Architecture (AMBA), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe) and Ethernet. A review of some protocol converter/translator are done with a view to explore their usability.

Ultra Low Power and High Efficiency Advanced Microcontroller Design using Amba Architecture

The ARM Advanced Microcontroller Bus Architecture (AMBA) is an open-criterion, on-chip interrelate particle particular in favor of the association also the board of useful squares in framework on a chip (SoC) plans. It encourages improvement of multi processor plans through expansive quantities of manager as well as peripherals among a transport design. Seeing as its commencement, the extent of AMBA has, regardless of its name, disappeared a long way past microcontroller gadgets. Nowadays, AMBA is broadly utilized on a scope of ASIC along with SoC divisions incorporating requests processors utilized in current convenient cell phones like advanced mobile phones. The structure comprises of at least one CPUs, GPUs or flag processors, autonomous, to permit reuse of IP centers, fringe and framework full scale cells crosswise over differing IC forms, supporting superior and low power on-chip correspondence.

Design and SV Based Verification of AMBA AXI Protocol for SOC Integration

Advanced Microcontroller Bus Architecture Advanced eXtensible Interface (AMBA AXI) provided by the ARM supports the high performance and high frequency system design. The System on Chip (SOC) Integration design needs to meet the low latency and high bandwidth challenges. The complex bridges are necessary when high frequency operations are carried out and there is a need for the interface which meets the requirement for the wide range of the applications, all such requirements without the complex bridges are provided by the AMBA AXI. The verification of such a bus protocol required to make the SOC integration most robust one. System Verilog based verification methodology provides the systematic way of verifying such a SOC to make it as a most reliable one. Also, SV based assertion makes the checking all the protocols specification easier at the verification stage. In the present paper, the general design and verification methodologies for the AXI-Bus and Memory interface for SOC integration is proposed. Verilog based memory and AXI design being done using Verilog HDL and design challenges are discussed. The proposed design implementation supports single and burst based data transfers. The AXI protocol provides the dedicated channels for memory read and write operations. In this work, single master and single slave communication using AXI protocol with 32-bit SARM are designed and implemented. The System Verilog based verification environment is setup and used for the verification IP development. And SV Assertion based verification is being done to thoroughly check the AXI protocol functionality.