Advanced Micro Devices Research Articles

Investment Research on Individual Stocks in Large Research Industry Enterprises

As technology continues to develop, the influence of the technology industry on the market cannot be ignored. This study aims to explore the trends and fluctuations of key representative technology stocks, specifically focusing on Advanced Micro Devices (AMD), Oracle Corporation (ORCL), and Qualcomm Incorporated (QCOM). By meticulously analyzing the publicly available balance sheets and income statements of these companies, we will extract pertinent financial indices and conduct a comprehensive financial analysis. The analysis will include key financial metrics such as revenue growth, profit margins, return on equity (ROE), and debt-to-equity ratios, among others. These metrics will be used to evaluate the financial health and performance trends of each company over a specified period. Additionally, we will compare these metrics across the three companies to provide insights into their relative market positions and competitive advantages. The objective of this analysis is to furnish investors with a reliable and data-driven market analysis that can inform their investment decisions. By understanding the financial underpinnings of these technology giants, investors can better assess the potential risks and returns associated with investing in these stocks. This study aims to bridge the gap between financial theory and practical investment strategies, offering a valuable resource for both individual and institutional investors interested in the technology sector.

A universal parallel simulation framework for energy pipeline networks on high-performance computers

Energy distribution networks represent crucial infrastructures for modern society, and various simulation tools have been widely used by energy suppliers to manage these intricate networks. However, simulation calculations include a large number of fluid control equations, and computational overhead limits the performance of simulation software. This paper proposes a universal parallel simulation framework for energy pipeline networks that takes advantages of data parallelism and computational independence between network elements. A non-pipe model of an energy supply network is optimized, and the input and output of the network model in the proposed framework are modified, which can reduce the development burden during the numerical computations of the pipeline network and weaken the computational correlation between different simulated components. In addition, independent computations can be performed concurrently through periodic data exchange procedures between component instances, improving the parallelism and efficiency of simulation computations. Further, a parallel water pipelines network simulation computing paradigm based on a heterogeneous computer hardware architecture is used to evaluate the proposed framework’s performance. A series of tests are conducted to verify the accuracy of the proposed framework, and simulation errors of less than 5% are achieved. The results of multi-threaded simulation experiments have demonstrated the feasibility of the proposed framework in a parallel computing approach. Moreover, an Advanced Micro Devices (AMD) Deep Computing Unit (DCU)-parallel program is implemented into a water supply network simulation system; the computational efficiency of this system is compared with that of its serial counterpart. The experimental results show that the proposed framework is appropriate for high-performance computer architectures, and the 18x speed-up ratio demonstrates that the parallel program based on the proposed universal framework outperforms the serial program. That provides the basis for the application of pipe network simulation on high-performance computers.

Deep multilevel wet etching of fused silica glass microstructures in BOE solution

Fused silica glass is a material of choice for micromechanical, microfluidic, and optical devices due to its chemical resistance, optical, electrical, and mechanical performance. Wet etching is the key method for fabricating of such microdevices. Protective mask integrity is a big challenge due extremely aggressive properties of etching solution. Here, we propose multilevel microstructures fabrication route based on fused silica deep etching through a stepped mask. First, we provide an analysis of a fused silica dissolution mechanism in buffered oxide etching (BOE) solution and calculate the main fluoride fractions like {HF}_{2}^{-}, {F}^{-}, {(HF)}_{2} as a function of pH and NH4F:HF ratio. Then, we experimentally investigate the influence of BOE composition (1:1–14:1) on the mask resistance, etch rate and profile isotropy during deep etching through a metal/photoresist mask. Finally, we demonstrate a high-quality multilevel over-200 μm etching process with the rate up to 3 μm/min, which could be of a great interest for advanced microdevices with flexure suspensions, inertial masses, microchannels, and through-wafer holes.

Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography

Fault detection is becoming greatly important in protecting cryptographic designs that can suffer from both natural or malicious faults. Finite fields over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> are widely used in such designs, since their data are coded in binary form for practical reasons. Among the different finite field arithmetic, multiplication is the bottleneck operation for many cryptosystems due to its complexity. Therefore, in this work, fault detection schemes based on cyclic codes for finite field multipliers using different fields found in traditional and post-quantum cryptography are derived. Moreover, we implement such schemes by embedding them into the original architectures to perform an exhaustive study, benchmark the different overheads obtained, and prove their suitability for deeply constrained embedded systems. These implementations are performed on advanced micro devices (AMD)/Xilinx field-programmable gate array (FPGA) and provide a very high error coverage with acceptable overhead.

Comparative thermal performance evaluation of a heat sink based on geometrical and material amendments: A numerical study

The study focuses on the design and materialistic amendments for thermal performance evaluation of a heat sink which is a just modified version of the conventional heat sink used for processor Ryzen 5 3600, introduced by a company named Advanced Micro Devices (AMD) for cooling applications in High-Performance Gaming PCs. The enhancement of the cooling strategy is achieved within dimensional and cost constraints by modifying the parametric dimensions, increasing the surface area, and introducing metal to the air-fluid boundary layer aspects into it. In this study, the heat sink is designed with a core of cylindrical shape, keeping a height of 20 mm and a diameter of 90 mm. Also, the universal dimensional compatibility of this heat sink is considered for the performance evaluation, followed by design and angle of air-fin interaction, swapped center rectangle shape with a frustum to decrease the thermal hindrance and to increase the surface area without any increment in overall volume. Moreover, the fin density in the module of the heat sink has also been increased to enhance the convective heat transfer strategy from the surface. Both designing & simulation have been carried out on the FEM tool Autodesk Fusion 360 and based on the numerical investigation on the modified design as per the conventional design, although our design is much more complex to manufacture in the first place. It has been observed that the new design is capable of providing 64.23% convective heat dissipation from the surface as well as able to reduce 50.9% of CPU surface temperature in comparison to the existing design of heat sink.

Trustees of Columbia Univ. in City of New York v. Illumina, Inc. United States Court of Appeals of the Federal Circuit, 2021 No. 2019-2302, 2021 WL 317661 (nonprecedential)

Trustees of Columbia Univ. in City of New York v. Illumina, Inc. United States Court of Appeals of the Federal Circuit, 2021 No. 2019-2302, 2021 WL 317661 (nonprecedential)

Cu Pillar Bump Development for 7-nm Chip Package Interaction (CPI) Technology

Abstract Power, performance, and area gains are important metrics driving the complementary metal–oxide–semiconductor (CMOS) technology from older nodes to newer ones. Over past several decades, a steady downscaling of feature sizes of CMOS technology has been a leading force enabling continual improvement in circuit speeds and cost per functionality. Increase in functionality drives larger number of inputs/outputs (I/Os), and the scaling-driven small intellectual property (IP) block sizes force these larger number of I/Os to be accommodated by reduction of I/O pitches. The result is an unrelenting pressure to reduce bump pitches from one generation of CMOS to another. In contrast to 14-nm/16-nm nodes which used 150-um bump pitch coming out of a die, for 7-nm node, the industry is targeting 130-um bump pitch for high performance devices. With this pitch reduction, conventional tin/silver (SnAg) solder bumps face limitations in terms of bridging. Cu pillar bumps are the best candidate for smaller bump pitches. However, for large die sizes prevalent in high-performance computing (HPC), the Cu pillar bumps will induce higher stress on the silicon resulting in higher risks of extremely low K (ELK) cracking. If copper pillar bumps are not properly developed, then there is a risk of marginal reliability in terms of chip package interaction. The situation becomes even more dire in large die sizes, where coefficient of thermal expansion mismatch between silicon and laminate substrate magnifies the stress. The present article discusses successful development of Cu pillar bumps for 7-nm technology. The development program included a 2-step development path. In the first step, extensive thermomechanical modeling was carried out to find optimal design of copper pillar bump for robustness of interactions with 7-nm back end of line ELK layers. In the second step, a 460-mm2 7-nm Silicon test vehicle was fabricated, and its assembly process was optimized to characterize the copper pillar bumps and prove their extended reliability on 7-nm silicon. As a result of this development, copper pillar technology has been qualified on Advanced Micro Devices (AMD) products. Today, copper pillar is a fully integral part of AMD's ever-growing 7-nm product offering in HPC.

Engineering mass transport properties in oxide ionic and mixed ionic-electronic thin film ceramic conductors for energy applications

New emerging disciplines such as Nanoionics and Iontronics are dealing with the exploitation of mesoscopic size effects in materials, which become visible (if not predominant) when downsizing the system to the nanoscale. Driven by the worldwide standardisation of thin film deposition techniques, the access to radically different properties than those found in the bulk macroscopic systems can be accomplished. This opens up promising approaches for the development of advanced micro-devices, by taking advantage of the nanostructural deviations found in nanometre-sized, interface-dominated materials compared to the “ideal” relaxed structure of the bulk. A completely new set of functionalities can be explored, with implications in many different fields such as energy conversion and storage, or information technologies. This manuscript reviews the strategies, employed and foreseen, for engineering mass transport properties in thin film ceramics, with the focus in oxide ionic and mixed ionic-electronic conductors and their application in micro power sources.

On-Line Temperature Estimation for Noisy Thermal Sensors Using a Smoothing Filter-Based Kalman Predictor.

Dynamic thermal management (DTM) mechanisms utilize embedded thermal sensors to collect fine-grained temperature information for monitoring the real-time thermal behavior of multi-core processors. However, embedded thermal sensors are very susceptible to a variety of sources of noise, including environmental uncertainty and process variation. This causes the discrepancies between actual temperatures and those observed by on-chip thermal sensors, which seriously affect the efficiency of DTM. In this paper, a smoothing filter-based Kalman prediction technique is proposed to accurately estimate the temperatures from noisy sensor readings. For the multi-sensor estimation scenario, the spatial correlations among different sensor locations are exploited. On this basis, a multi-sensor synergistic calibration algorithm (known as MSSCA) is proposed to improve the simultaneous prediction accuracy of multiple sensors. Moreover, an infrared imaging-based temperature measurement technique is also proposed to capture the thermal traces of an advanced micro devices (AMD) quad-core processor in real time. The acquired real temperature data are used to evaluate our prediction performance. Simulation shows that the proposed synergistic calibration scheme can reduce the root-mean-square error (RMSE) by 1.2 C and increase the signal-to-noise ratio (SNR) by 15.8 dB (with a very small average runtime overhead) compared with assuming the thermal sensor readings to be ideal. Additionally, the average false alarm rate (FAR) of the corrected sensor temperature readings can be reduced by 28.6%. These results clearly demonstrate that if our approach is used to perform temperature estimation, the response mechanisms of DTM can be triggered to adjust the voltages, frequencies, and cooling fan speeds at more appropriate times.

Quaternary Co1−x−yZnxCdyS thin films: A facile synthesis approach and its aptness for the applications in micro-devices

The synthesis of multicomponent semiconducting thin films has become the subject of intensive research. The development of deposition-characterization techniques and property correlation and understanding of these materials are critical for the successful implementation of a whole new generation of advanced micro-devices. A wide range of discussion made in this article include facile chemical synthesis of Zn, Cd(CoS) thin films and characterization pertaining to the studies on compositional, morphological, optical and electrical transport aspects. The overall discussion involved herein will be useful to establish further engrossment of the researchers in the mentioned quaternary system.

Direct Fabrication of Microlens Arrays on PMMA With Laser-Induced Structural Modification

Reported here is the direct fabrication of the convex microlens arrays on poymethylmethacrylate using laser-induced structural modification. Based on single femtosecond pulse in situ modification, sixty thousand convex microlenses, whose diameters was $ , could be fabricated per minute, exhibiting much higher efficiency than conventional laser direct writing technique. The formation mechanism was mainly attributed to photodecomposition, which would result in the scission of polymer chains. The shape of microlenses could be tuned by the laser power. In addition, the good optical performance of the microlens was revealed by its ability of high resolution imaging. This technique may open up a new way of preparing low-cost and large-area convex structure which is widely used in many advanced microdevices, such as lab-on-chips and biomimetic compound eyes.

Technology Moving Beyond Any Boundaries

The smartphone business has long been regarded as the overall growth market. The young market has concord in record speed the entire world and is an integral part of today's society. There are also companies behind the scenes who have more to offer. A good example is Qualcomm. Advanced Micro Devices (AMD) is the second-largest chipmaker after Intel. In the field of online retail Amazon you can now hardly thought away. The company is the undisputed top dog. That could change in the future. In the house apparently Google is planning even strengthened to go into the online shopping business. Only few stocks attract investors into its spell - just because of the name. At Apple, it is so for years - but the US cult company has provided extremely good record data. On Facebook there is similar. The two technology giants have discovered the self-propelled car as a growth area independently. Already in 2020 an annual turnover of over 100 billion Euros is to be achieved in this area. Google and Apple want to save each a large piece of the pie.

A holistic model of the performance and the energy efficiency of hypervisors in a high‐performance computing environment

SUMMARYVirtualization is emerging as the prominent approach to mutualise the energy consumed by a single server running multiple virtual machines instances. The efficient utilisation of virtualized servers and/or computing resources requires understanding of the overheads in energy consumption and the throughput especially on high‐demanding high‐performance computing (HPC) platforms. In this paper, a novel holistic model for the power of virtualized computing nodes is proposed. Moreover, we create and validate instances of the proposed model using concrete measures taken during a benchmarking process that reflects an HPC usage, that is, HPC challenge, IOZone and Bonnie++, conducted using two different hardware configurations on Grid'5000 platform, based on Intel and Advanced Micro Devices (AMD) processors and three widespread virtualization frameworks, namely, Xen, Kernel‐based virtual machine and VMware ESXi. The proposed holistic model of machine power takes into account the impact of utilisation metrics of the machine's components, as well as the employed application, virtualization and hardware. The model is further derived using tools such as multiple linear regressions or neural networks that prove its elasticity, applicability and accuracy. The purpose of the model is to enable the estimation of energy consumption of virtualized platforms, aiming to make possible the optimization, scheduling or accounting in such systems or their simulation. Copyright © 2014 John Wiley &amp; Sons, Ltd.

Analysis of advanced photonic devices with time-dependent coupled mode equations

Based on the recently proposed time-dependent coupled mode theory (TD CMT) for parallel waveguides, we present an analysis of three advanced photonic micro-devices: micro-interferometer, 90-deg bent, and a tunable beam splitter. An accurate analysis of these devices with commercial software may take many hours, whereas the TD CMT needs only minutes with little sacrifice of accuracy.

Parallelizing a Black‐Scholes solver based on finite elements and sparse grids

SUMMARYWe present the parallelization of a sparse grid finite element discretization of the Black–Scholes equation, which is commonly used for option pricing. Sparse grids allow to handle higher dimensional options than classical approaches on full grids and can be extended to a fully adaptive discretization method. We introduce the algorithmical structure of efficient algorithms operating on sparse grids and demonstrate how they can be used to derive an efficient parallelization with OpenMP of the Black–Scholes solver. We show results on different commodity hardware systems based on multi‐core architectures with up to 24 cores and discuss the parallel performance using Intel and Advanced Micro Devices (AMD) CPUs. Copyright © 2012 John Wiley &amp; Sons, Ltd.

Multifunctional nanomembranes self-assembled into compact rolled-up sensor–actuatordevices

This paper reports on the functional principle for a rolled-up microdevice family providingthe possibility to realise electrical sensor and actuator functions which are applicable tomicrosystem techniques, in the field of physical measuring techniques, microfluidics andbiological–medical analytics. The fabrication of the roll-up devices is based ona strain-driven process converting a planar two-dimensional membrane into athree-dimensional functional element. For the realisation of these roll-up structures a broadspectrum of thin film technological approaches were used, which are well established. Thespecial feature of these advanced microdevices consists in the possibility to design thelatter’s inner surface using established additive or subtractive thin film techniques. Thetechnological route elaborated in the present work could possibly be used to realise a valvefor microfluidics thanks to the combined advantages of rolled-up devices andthe unique properties of temperature-sensitive hydrogels. Due to the thermaldecoupling of the processed microheaters from the supporting substrate the obtainedmicrodevices obtained are superior to conventional miniaturised planar devices in theirgeneral performance, especially in respect to the dynamical behaviour of thethermal properties. This is a prospective basis for the conceptual creation ofcombined sensor/actuator devices with tailored electrical and thermal properties.

Microfluidics for bacterial chemotaxis

Microfluidics is revolutionizing the way we study the motile behavior of cells, by enabling observations at high spatial and temporal resolution in carefully controlled microenvironments. An important class of such behavior is bacterial chemotaxis, which plays a fundamental role in a broad range of processes, including disease pathogenesis, biofilm formation, bioremediation, and even carbon cycling in the ocean. In biophysical research, bacterial chemotaxis represents a powerful model system to understand how cells and organisms sense and respond to gradients. Using microfluidics to study chemotaxis of free-swimming bacteria presents experimental challenges that are distinct from those arising in chemotaxis studies of surface-adherent cells. Recently, these challenges have been met by the development of advanced microdevices, able to generate flow-free, steady gradients of arbitrary shape. Much attention to date has been focused on tool development. Yet, we are now at an exciting turning point where science begins to balance technology. Indeed, recent microfluidic studies provided new insights on both the mechanisms governing bacterial gradient sensing (e.g. tuning of response sensitivity, discrimination between conflicting gradients) and the large-scale consequences of chemotaxis (e.g. in the oceans). Here we outline the principles underlying recently proposed gradient generators for bacterial chemotaxis, illustrate the advantage of the microfluidic approach through selected examples, and identify a broader set of scientific questions that may now be addressed with this rapidly developing technology. The latest generation of microfluidic gradient generators, in particular, holds appeal for both biophysicists seeking to unravel the fundamental mechanisms of bacterial chemotaxis, and ecologists wishing to model chemotaxis in realistic environments. Time is ripe for a deeper integration between technology and biology in fully bringing to bear microfluidics on studies of this fascinating microbial behavior.

In this issue: Biotechnology Journal 11/2009

AbstractForensic identification on chipsChoi and Seo et al., Biotechnol. J. 2009, 4, 1530–1541Short tandem repeat (STR) analysis can be used for genetic fingerprinting of individuals as it is done for forensic human identification. However, the current state‐of‐the‐art STR genotyping processes and instruments are labor intensive, expensive, time consuming, and lack portability. Micro‐total‐analysis systems or lab‐on‐a‐chip platforms based on microfabrication technologies have the capability to miniaturize and integrate bioanalysis steps in a single format and have already been successfully applied for forensic STR typing. Researchers from Daejeon, Korea, highlight up‐to‐date work on advanced microdevices for high‐throughput STR genotyping, and a portable integrated microsystem for on‐site forensic DNA analysis.Surface plasmon resonance on chipsMaynard et al., Biotechnol. J. 2009, 4, 1542–1558Technologies based on surface plasmon resonance (SPR) have allowed rapid, label‐free characterization of protein‐protein and protein‐small molecule interactions. SPR has become the gold standard in industrial and academic settings, in which the interaction between a pair of soluble binding partners is characterized in detail or a library of molecules is screened for binding against a single soluble protein. In spite of these successes, SPR is only beginning to be adapted to the needs of membrane‐bound proteins which are promising targets for drug and biomarker development. This team of authors from Austin, Minneapolis and Rochester (all USA) describe current SPR instrumentation and the potential for SPR nanopore arrays to enable quantitative, high‐throughput screening of G‐protein coupled receptor ligands and applications in cellular biology.Nucleotide immobilization on chipsSethi et al., Biotechnol. J. 2009, 4, 1513–1529The development of oligonucleotide‐based microarrays (biochips) is of major interest in science and biotechnology industry and has applications in a wide range of research areas including genomics, proteomics, computational biology and pharmaceuticals. Especially microarrays have proven to be a unique method for time and cost efficient analysis of thousands of genes at one. Authors from Delhi and Lucknow, India discuss currently used chemical strategies for immobilization of oligonucleotides and put a special emphasis on post‐synthetic immobilization on glass surfaces. Recent advances on these synthesis pathways are presented in detail.

An integrated microdevice for high‐performance short tandem repeat genotyping

Short tandem repeat (STR) analysis provides genetic fingerprinting of individuals, and is considered as a powerful and indispensable technique for forensic human identification. However, the current state-of-the-art STR genotyping processes and instruments are labor intensive, expensive, time consuming, and lack portability. Micro-total-analysis systems or lab-on-a-chip platforms based on microfabrication technologies have the capability to miniaturize and integrate bioanalysis steps in a single format. Recent progress in microsystems has demonstrated their successful performance for the forensic STR typing with a reduced cost, high speed, and improved high throughput. The purpose of this review article is to highlight up-to-date work on advanced microdevices for high-throughput STR genotyping, and a portable integrated microsystem for on-site forensic DNA analysis.

Acceleration of cardiac tissue simulation with graphic processing units

In this technical note we show the promise of using graphic processing units (GPUs) to accelerate simulations of electrical wave propagation in cardiac tissue, one of the more demanding computational problems in cardiology. We have found that the computational speed of two-dimensional (2D) tissue simulations with a single commercially available GPU is about 30 times faster than with a single 2.0 GHz Advanced Micro Devices (AMD) Opteron processor. We have also simulated wave conduction in the three-dimensional (3D) anatomic heart with GPUs where we found the computational speed with a single GPU is 1.6 times slower than with a 32-central processing unit (CPU) Opteron cluster. However, a cluster with two or four GPUs is faster than the CPU-based cluster. These results demonstrate that a commodity personal computer is able to perform a whole heart simulation of electrical wave conduction within times that enable the investigators to interact more easily with their simulations.