Advanced Logic Research Articles

(Invited) Trends in 3D Markets and Technology

Driven by performance, 3D packaging with through silicon vias (TSVs) has become a reality for memory and advanced logic. New versions are emerging. High Bandwidth Memory (HBM) is one of the most important 3D IC developments in the last 10 years. In the last decade, stacked DRAM with through silicon vias has transitioned from a handful of research programs to rapidly increasing volumes. Tezzaron has been providing small quantities of 3D ICs for high-speed memory applications since 2005. Micron, Samsung, and SK Hynix began producing DRAM stacks with TSVs in late 2014 and early 2015. Micron began shipments of its Hybrid Memory Cube (HMC) in 2015. DRAMs and the logic controller were interconnected with TSVs. HMC was packaged in a BGA and tested before assembly on the board. The HMC has been used in Intel’s Knights Landing. The silicon-on-insulator (SOI) logic layer was fabricated by GLOBALFOUNDRIES (which purchased IBM’s fab) and the memory was fabricated by Micron. Micron used a thermo-compression bond (TCB) process with a non-conductive film (NCF) underfill for its die stacking in the HMC. Thermal issues were a challenge. Today Samsung and SKHynix are providing HBM stacks to the industry and Micron is expected to ship products next year. In February 2018, Samsung announced that its first “three-layer” stacked CMOS image sensors (CIS) were in mass production and found in the Galaxy S9/S9+. This follows Sony’s adoption of three-layer CIS technology one year earlier in February 2017. A third silicon layer in the form of DRAM is added to the pixel array and signal processing layers to significantly improve data readout speeds. These devices are manufactured with 3D IC technologies using TSVs, but Samsung and Sony use different design approaches. Technically speaking, Samsung’s solution is a two-layer image sensor with a stacked DRAM. Sony uses a true three-layer bonded approach. In its three-layer CIS technology, Sony places the DRAM between the pixel array die and the image processor, with all three layers interconnected using TSVs. The pixel array, DRAM, and logic wafers are manufactured with 90nm, 30nm, and 40nm processes, respectively. While logic and memory stacks have remained elusive, Intel and TSMC have introduced new packaging technology with active interposers that are considered 3D. Intel has introduced its Foveros 3D integration technology as a form of heterogeneous system integration. The technology uses a 3D face-to-face stacking process. In the process, logic die are bumped and mounted on an active interposer next to memory or die with other functions. The active interposer can contain active parts of the system, such as the platform controller hub (PCH) that manages I/O for the system. The active interposer is mounted on a package substrate with solder bumps. TSMC has introduced its SoIC with face-to-face stacking and wafer-on-wafer (WoW). These technologies are front-end packaging and use direct or fusion bonding. The SoIC is a wafer with logic, with our without TSVs.

(Invited) Atomic Layer Processing for Advanced Electronics

With devices and interconnects now being scaled to below the limits of even the most advanced lithographic patterning, dimensional control requires new thin-film processes with atomic-scale control of thickness, uniformity, morphology, and material and electrical properties at all levels, from the atomic scale to the equipment scale. With ever increasing complexity in process technologies, chemically selective and/or area-selective processes can be an efficient way to meet future manufacturing requirements. Novel process technologies are needed for deposition, etch and cleans with atomic level precision to enable area-selective-processing at the structure and material level [1]. In this tutorial we will review and discuss trends in Atomic Layer Processing technologies for advanced semiconductor device manufacturing. The topics and technologies explored in this presentation include atomic layer deposition (ALD), atomic layer etching (ALE), selective deposition and etching, advanced surface preparation, EUV lithography, and self-aligned and multiple patterning schemes among others. Applications include critical material and manufacturing challenges for advanced Logic and Memory devices, including high-k oxides and metals, interconnects, capacitors, as well as Patterning, including Multi Patterning, Fully-Self-Aligned patterning and EUV [2]. A key point of this presentation will be to educate attendees how these advanced process technologies can be leveraged synergistically to deliver power, performance, area and cost scaling for future devices. Examples will be given so that attendees can understand how advanced process technologies will be used in future device manufacturing as well as the benefits and tradeoffs in their use.

Symbolic Analysis of Maude Theories with Narval

AbstractConcurrent functional languages that are endowed with symbolic reasoning capabilities such as Maude offer a high-level, elegant, and efficient approach to programming and analyzing complex, highly nondeterministic software systems. Maude’s symbolic capabilities are based on equational unification and narrowing in rewrite theories, and provide Maude with advanced logic programming capabilities such as unification modulo user-definable equational theories and symbolic reachability analysis in rewrite theories. Intricate computing problems may be effectively and naturally solved in Maude thanks to the synergy of these recently developed symbolic capabilities and classical Maude features, such as: (i) rich type structures with sorts (types), subsorts, and overloading; (ii) equational rewriting modulo various combinations of axioms such as associativity, commutativity, and identity; and (iii) classical reachability analysis in rewrite theories. However, the combination of all of these features may hinder the understanding of Maude symbolic computations for non-experienced developers. The purpose of this article is to describe how programming and analysis of Maude rewrite theories can be made easier by providing a sophisticated graphical tool called Narval that supports the fine-grained inspection of Maude symbolic computations.

Context-aware parallel handover optimization in heterogeneous wireless networks

The key idea of this paper is to a use cross-layer triggering concept in order to control the vertical handover (VHO) in heterogeneous networks. Current mobility management protocols could not handle the ever-growing quality of service (QoS) demand for connected mobile nodes (MNs). Motivated by addressed challenging problems, the proposed multi-layer parallel handover optimization (MPHO) is capable of handling application awareness in its decision process. Each layer in the protocol stack implements its own decision mechanisms in response to environmental changes. Independent decisions may lead to un-optimal operation while reacting to the same event. MPHO coordinates triggered actions using a centralized controller. MPHO utilizes dynamic attributes to reduce HO latencies and signaling overheads with a more advanced coordination logic. It contains a prediction module that utilizes MN mobility patterns. Evaluation results validate the achieved enhancements with a smaller HO failure rate and increased throughput. MPHO achieves improvements in terms of perceived quality and delay constraints.

(Invited) Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges

This paper addresses the opportunities and challenges of wet and dry selective etches in the integration of gate-all-around (GAA) field-effect transistor (FET), which is emerging as a promising solution to replace FinFET for the advanced logic devices. For the GAA device fabrication, a quintessential challenge is a controlled isotropic etching of dielectrics, semiconductors, and metals with high selectivity to the exposed materials. In this paper, the significance of the unit process modules in the GAA device integration: shallow trench isolation (STI), inner spacer formation, replacement metal gate (RMG) and self-aligned interconnect in the middle-of-line (MOL) and the back-end-of-line (BEOL), will be discussed.

Low-cost implementation and characterization of an active phasor data concentrator

The main components of an advanced measurement system based on synchrophasor technology for the monitoring of power systems are the phasor measurement unit (PMU), which represents the ‘sensor’, and the phasor data concentrator (PDC), which collects the data forwarded by PMUs installed on the field. For the purpose of extending the benefit of synchrophasor technology from transmission grids to distribution networks, different projects are seeking to use low-cost platforms to design devices with PMU functionalities. In this perspective, in order to achieve a complete synchrophasor-based measurement architecture based on low-cost technologies, this work presents a PDC design based on a low-cost platform. Despite the simplicity of the considered hardware, advanced PDC functionalities and innovative control logics are implemented in the prototype. The proposed device is characterised by several experimental tests aimed at assessing its performance in terms of both time synchronisation and capability of managing several PMU data streams. The feasibility of some additional functionalities and control logics is evaluated in the context of different possible scenarios.

Probe computing model based on small molecular switch

BackgroundDNA is a promising candidate for the construction of biological devices due to its unique properties, including structural simplicity, convenient synthesis, high flexibility, and predictable behavior. And DNA has been widely used to construct the advanced logic devices.ResultsHerein, a molecular probe apparatus was constructed based on DNA molecular computing to perform fluorescent quenching and fluorescent signal recovery, with an ’ ON/OFF’ switching function. In this study, firstly, we program the streptavidin-mediated fluorescent quenching apparatus based on short-distance strand migration. The variation of fluorescent signal is acted as output. Then DNAzyme as a switching controller was involved to regulate the fluorescent signal increase. Finally, on this base, a cascade DNA logic gate consists of two logic AND operations was developed to enrich probe machine.ConclusionThe designed probe computing model can be implemented with readout of fluorescence intensity, and exhibits great potential applications in the field of bioimaging as well as disease diagnosis.

Versatile and Homogeneous DNA Tetraplex Platform for Constructing Label-Free Logic Devices: From Design to Application.

The design of DNA-based logic circuits has become an active research field in DNA nanotechnology and holds great potential in intelligent bioanalysis. To date, although many DNA-based logic systems have been realized, the implementation of advanced logic functions is still challenging, especially with simple and homogeneous compositions. Herein, by integrating two DNA tetraplex structures (G-quadruplex and i-motif), a completely label-free logic platform with high scalability was established, with which a series of advanced functions were realized, including arithmetic (adders and subtractors) and nonarithmetic ones (majority and dual-transfer gates). Furthermore, the platform was also applied as an intelligent biosensor to coanalyze two cancer-related micro-RNAs with high sensitivities and specificities. Considering the excellent versatility, expandability, and biocompatibility, the platform may promote the development of DNA computing and hold great potential in multiparameter sensing and medical diagnosis.

(Invited) Enabling 5nm and Beyond Device Fabrication with New Etch Technologies

All logic device roadmaps predict significant change in the form and nature of logic at 5 nm. III-V’s, SiGe, Ge, nanowires and nano-sheets, while attractive as device options, bring pause to process and integration teams that need to integrate new materials or new material forms. Research grade devices are certainly possible today but high volume manufacturing of new devices in whatever form they may take requires change to unit processes available in today’s fabrication facilities. The question is whether something entirely new is needed or it is a matter of enhancing the capabilities of process and equipment that exists today. A key of those responsible for next generation logic is damage in one form or another by the (plasma) etch unit process. III-V’s, SiGe and Ge devices are particularly sensitive to damage. This has motivated calls for a complete move to thermal etch processes potentially upending available integration approaches. Unfortunately, thermal processes are themselves not damage free in that it is impossible not to leave interfaces and the immediate sub-surfaces unaltered. Fortunately, advances in plasma etch technology allow plasma etch to meet and exceed thermal process performance. Pulsing technology went a long way to mitigating damage caused during silicon device fabrication more than a decade ago. Now, advanced pulse technology applied to advanced plasma sources delivers performance equivalent to thermal processes by precise control of surface passivation, surface volatilization and surface reaction by-products. Concurrent advances in applying novel process chemistries (plasma based self-limited material removal and deposition processes) are also ready for new logic materials. Key is the availability of advanced materials chemistry simulations for use in process development. The research opportunities for new etch technology for “selective area etching” in advanced logic manufacturing will be the next frontier of R&D activities.

Area‐efficient and high‐speed hardware structure of hybrid cryptosystem (AES‐RC4) for maximizing key lifetime using parallel subpipeline architecture

SummaryWith the growth of wireless environments, confidential communication has become an important part of daily life. Generally, a wireless medium uses cryptography techniques when transmitting data to provide end‐to‐end protection. Most of the hardware‐efficient cryptosystems do not satisfy the security requirements. In this paper, we concentrate both on security issues and hardware efficiency and present an area‐efficient, high‐throughput hardware structure to implement a hybrid cryptosystem to avoid security problems. The security enhancements are done using a key enhancement process, and it is achieved by using a hybrid encryption cryptosystem. In this paper, we combine block and stream cipher encryption algorithms to frame the hybrid algorithm. We consider advanced encryption standard (AES) as the block cipher and Rivest cipher‐4 (RC4) as the stream cipher. Due to the hybrid systems, performance metrics, such as area, throughput, and power consumptions, are affected. Moreover, advanced arithmetic logic (ie, field arithmetic) combined with the on‐the‐fly key expansion technique is used to minimize area consumption, and parallel subpipeline technique is used to enhance the system throughput. The proposed hybrid architecture (AES‐RC4) is implemented in a field‐programmable gate array with a Xilinx tool.

Safety analysis of plugging and abandonment of oil and gas wells in uncertain conditions with limited data

Well plugging and abandonment are necessitated to ensure safe closure of a non-producing offshore asset. Little or no condition monitoring is done after the abandonment operation, and data are often unavailable to analyze the risks of potential leakage. It is therefore essential to capture all inherent and evolving hazards associated with this activity before its implementation. The current probabilistic risk analysis approaches such as fault tree, event tree and bowtie though able to model potential leak scenarios; these approaches have limited capabilities to handle evolving well conditions and data unavailability. Many of the barriers of an abandoned well deteriorates over time and are dependent on external conditions, making it necessary to consider advanced approaches to model potential leakage risk. This paper presents a Bayesian network-based model for well plugging and abandonment. The proposed model able to handle evolving conditions of the barriers, their failure dependence and, also uncertainty in the data. The model uses advanced logic conditions such as Noisy-OR and leaky Noisy-OR to define the condition and data dependency. The proposed model is explained and tested on a case study from the Elgin platform's well plugging and abandonment failure.

NanoElectronics roadmap for Europe: From nanodevices and innovative materials to system integration

The NEREID project (“NanoElectronics Roadmap for Europe: Identification and Dissemination”) is dedicated to mapping the future of European Nanoelectronics. NEREID’s objective is to develop a medium and long term roadmap for the European nanoelectronics industry, starting from the needs of applications to address societal challenges and leveraging the strengths of the European eco-system. The roadmap will also identify promising novel nanoelectronic technologies, based on the advanced concepts developed by Research Centres and Universities, as well as identification of potential bottlenecks along the innovation (value) chain. Industry applications include Energy, Automotive, Medical/Life Science, Security, loT, Mobile Convergence and Digital Manufacturing. The NEREID roadmap covers Advanced Logic and Connectivity, Functional Diversification (Smart Sensors, Smart Energy and Energy for Autonomous Systems), Beyond-CMOS, Heterogeneous Integration and System Design as well as Equipment, Materials and Manufacturing Science. This article gives an overview of the roadmap’s structure and content.

P-N Junction Diode Using Plasma Boron-Doped Black Phosphorus for High-Performance Photovoltaic Devices.

This study used a spatially controlled boron-doping technique that enables a p-n junction diode to be realized within a single 2D black phosphorus (BP) nanosheet for high-performance photovoltaic application. The reliability of the BP surface and state-of-the-art 2D p-n heterostructure's gated junctions was obtained using the controllable pulsed-plasma process technique. Chemical and structural analyses of the boron-doped BP were performed using X-ray photoelectron spectroscopy, transmission electron microscopy, and first-principles density functional theory (DFT) calculations, and the electrical characteristics of a field-effect transistor based on the p-n heterostructure were determined. The incorporated boron generated high electron density at the BP surface. The electron mobility of BP was significantly enhanced to ∼265 cm2/V·s for the top gating mode, indicating greatly improved electron transport behavior. Ultraviolet photoelectron spectroscopy and DFT characterizations revealed the occurrence of significant surface charge transfer in the BP. Moreover, the pulsed-plasma boron-doped BP p-n junction devices exhibited high-efficiency photodetection behavior (rise time: 1.2 ms and responsivity: 11.3 mA/W at Vg = 0 V). This study's findings on the tunable nature of the surface-transfer doping scheme reveal that BP is a promising candidate for optoelectronic devices and advanced complementary logic electronics.

DEVELOPMENT OF FUZZY LOGIC APPROACH TO OPTIMIZE SAFETY STOCK LEVEL IN DETERIORATED PRODUCTS/A SUPPLY CHAIN DAIRY INDUSTRIES CASE STUDY

In today's complex environment, a high responding ability represents a core for each organization to survive in a competitive environment. To grip your position in intense competition market, the organization must design high efficiency inventory system that has the ability to respond to changes in demand and at the same time reduce holding cost of accommodation to the lowest possible value by controlling inventory drivers such as safety stock level (SS). The traditional approaches of safety stock are limited to deal with dynamic behavior of market. Advanced approaches based on soft computing allow the dynamic updating of SS level. In this paper, a highly advanced dynamic fuzzy logic (DFL) has been suggested as an innovation step to identify safety stock level in dairy industries with objective of minimizing total cost and meet with customer requirements. The proposed approach consists of three main steps firstly, identifying demand uncertainty conditions by applying fuzzy logic steps embedded by identifying dynamic (N) factor which represents the increasing level in demand in period time. Secondly, identifying of raw material availability conditions by applying fuzzy logic steps, and finally, identification of inventory on hand conditions by applying fuzzy logic steps. It is necessary to identify the level of SS dynamically in fuzzy logic as an output embedded with identifying of period specification concept which describes states of demand in a specific period in which the demand is high, medium, or low which leads to identify maximum values of universe of discourse of output (safety stock). Here Matlab program was used. The provided solution demonstrates the proposed model validity. There has been a significant reduction in safety stock level ranging from (7-98)% depending on product type and period specification with a reduction also in holding cost, while keeping the requirements fulfillment of customers demand

A differentially selective probe for trivalent chemosensor upon single excitation with cell imaging application: potential applications in combinatorial logic circuit and memory devices.

A new rhodamine 6G-benzylamine-based sensor (L1), having only hydrocarbon skeletons in the extended part, was synthesized and characterized by single-crystal X-ray crystallographic study. It exhibited excellent selective and sensitive recognition of trivalent metal ions M3+ (M = Fe, Al and Cr) over mono- and di-valent and other trivalent metal ions. A large enhancement of the fluorescence intensity for Fe3+ (41-fold), Al3+ (31-fold) and Cr3+ (26-fold) was observed upon the addition of 3.0 equivalent of these metal ions into the probe in H2O/CH3CN (4 : 1, v/v, pH 7.2) with naked eye detection. The corresponding Kf values were evaluated to be 9.4 × 103 M-1 (Fe3+), 1.34 × 104 M-1 (Al3+) and 8.7 × 103 M-1 (Cr3+). Quantum yields of the L1, [L1-Fe3+], [L1-Al3+] and [L1-Cr3+] complexes in H2O/CH3CN (4 : 1, v/v, pH 7.2) were found to be 0.012, 0.489, 0.376 and 0.310, respectively, using rhodamine-6G as standard. LODs for Fe3+, Al3+ and Cr3+ were determined by 3σ methods and found to be 1.28, 1.34 and 2.28 μM, respectively. Cyanide ion scavenged Fe3+ from the [Fe3+-L1] complex and quenched its fluorescence via its ring-closed spirolactam form. Advanced level molecular logic devices using different inputs (2 and 4 inputs) as advanced level logic gates and memory devices were constructed. The large enhancement in fluorescence emission of L1 upon complexation with M3+ metal ions makes the probe suitable for the bio-imaging of M3+ (M = Fe, Al and Cr) in living cells.

The FogDevices platform - a comprehensive hardware solution for IoT applications

This article presents the FogDevices hardware platform. It is a comprehensive set of concepts, approaches, and solutions for fast and effective IoT node hardware and software development. The proposed solution may contribute to more effective embedded IoT node software development by providing a unique tool for emulating environmental conditions. It is especially useful in development and testing of advanced data processing algorithms and operation logic for environmental conditions monitoring. By using the discussed approach, engineers can set up highly customized IoT hardware for operation in specific usage scenarios but without an excessive amount of work. The complete functional, electrical, and mechanical solution is presented along with multiple test results of its practical implementation.

Environmental Effects on Post-CMP PVAc Brush Releasable Contamination and Break-In Optimization for Advanced Logic and Memory Technologies

Advanced sub-7nm logic and VNAND memory technologies are becoming more reliant on Chemical Mechanical Planarization (CMP). New layers and materials are being introduced with each new technology node and integration scheme. Polyvinyl-acetal (PVAc) brushes are used extensively for post-CMP contact cleaning and remain the most reliable method for efficient cleaning of slurry residues while minimizing physical damage to sensitive films and structures. The releasable contamination from the virgin PVAc brush, however, is becoming more of an issue with each new technology node often affecting the yield of the device being manufactured. As a result, users are required to “break-in” or pre-condition brushes much longer than before to meet the required defect performance for these technologies. Longer PVAc brush break-in times negatively impact CMP tool utilization and overall equipment efficiency (OEE). This work attempts to characterize PVAc brush releasable contamination sources under simulated post-CMP cleaning conditions and suggests ways to reduce the break-in burden. Liquid particles (LPCs) were analyzed in the brush effluent and samples were subsequently dried and characterized by Fourier-transform infrared spectroscopy (FTIR). Environmental effects such as brush handling, temperature cycling, and dehydration, as well as post-CMP chemistry acclimation were all deemed significant contributors to the final releasable contamination profile and break-in characteristics of the brush. The brush Pore Templating Agent (PTA) represented the largest contribution of particles early in the brush lifetime. Loose PVAc particles were also a significant source of brush releasable contamination. PTA residue appears to decreases rapidly during brush use, whereas PVAc particulates reduce at a slower rate and eventually become the primary source of liquid particles. The physical nature of the post-CMP process and surface changes observed on the brush nodule are evidence that PVAc particulate reduction is largely unavoidable. PVAc brush break-in times, nevertheless, were accelerated by more aggressive break-in conditions and the application of chemistries known to improve the hydrolysis and removal of PTA. Offline but onsite PVAc brush break-in may be the most effective way to recover CMP tool utilization while minimizing environmental and chemistry acclimation effects simultaneously.

Retraction: A simple rhodamine-based dual signalling reversible molecular switch for recognition of Al(iii) with promising applications for advanced logic operations – ‘OR’, ‘Keypad Lock’ & ‘INHIBIT’ logic function and cell-imaging studies

Retraction of ‘A simple rhodamine-based dual signalling reversible molecular switch for recognition of Al(iii) with promising applications for advanced logic operations – ‘OR’, ‘Keypad Lock’ & ‘INHIBIT’ logic function and cell-imaging studies’ by Tarun Mistri et al., Analyst, 2014, DOI: 10.1039/C3AN02255B.

Metal ion-induced coordination and cyclization of crown ether-based bisindolylmaleimides: different fluorescence responses and applications in complex logical operations

Bisindolylmaleimide derivatives with crown ether display different interaction mechanisms with metal ions: coordination and oxidative cyclization, causing red and green emission, respectively, which can be used to construct advanced logic systems.

Design of DNA-based innovative computing system of digital comparison

Despite great potential and extensive interest in developing biomolecule-based computing, the development of even basic molecular logic gates is still in its infancy. Digital comparator (DC) is the basic unit in traditional electronic computers, but it is difficult to construct a system for achieving large-scale integration. Here, we construct, for the first time, a novel logic computing system of DCs that can compare whether two or more numbers are equal. Our approach is by taking advantage of facile preparation and unique properties of graphene oxide and DNA. The DC system reported in this work is developed by the DNA hybridization and effective combination of GO and single-stranded DNA, which is regarded as the reacting platform. On the basis of this platform and reaction principle, we have developed 2-inputs, 3-inputs, and 4-inputs DCs to realize the comparison of two or more binary numbers. We predict that such a state-of-the-art logic system enables its functionality with large-scale input signals, providing a new direction toward prototypical DNA-based logic operations and promoting the development of advanced logic computing. Statement of SignificanceThe overarching objective of this paper is to explore the construction of a novel DNA computing system of digital comparator driven by the interaction of DNA and graphene oxide (GO). GO can efficient bind the dye-labeled, single-stranded DNA probe and then quench its fluorescence. In the case of the target appearing, specific binding between the single-stranded probe and its target occurs, changing the conformation and relationship with GO, then restoring the fluorescence of the dye. We have developed the 2-inputs, 3-inputs, and 4-inputs digital comparator circuits, which are expected to realize the comparison of large-scale input signals and can avoid the problems of design complexity and manufacturing cost of integrated circuits in traditional computing.