Advanced High-performance Bus Research Articles

Green Computing: Crafting A Low-Energy Amba APB Bridge Solution

Abstract—The Advanced High-performance Bus (AHB), a key component of the Advanced Microcontroller Bus Architecture (AMBA) family, stands as a high-performance, low-power, and high- bandwidth communication interface within system components. Bridging to low-bandwidth peripherals, the Advanced Peripheral Bus (APB) offers a simple, non-pipelined protocol for read- and-write communication, linking a bridge/master to numerous slaves via a shared bus. The AHB to APB bridge serves a critical role in integrating diverse bus protocols, facilitating efficient communication between high-performance processing units and slower peripherals, thereby enhancing the System-on-Chip (SoC)'s overall effectiveness and functionality. This approach addresses the functional verification of the AMBA AHB to APB Bridge protocol with a focus on completeness. We employ a layered testbench architecture in System Verilog to ensure thorough verification of functionality with maximal coverage. Our verification environment is constructed using System Verilog, and simulations are conducted on the EDA playground platform. Through this comprehensive approach, we aim to provide robust validation of the AHB to APB bridge protocol, ensuring its reliability and compatibility within complex SoC designs. Keywords— Advanced Peripheral Bus (APB), System-On-Chip (SOC), Advanced Microcontroller Bus Architecture.

Design of Advanced High Performance Bus (AHB) to Advanced Peripheral Bus (APB) Bridge

The Advanced Microcontroller Bus Architecture (AMBA) has long served as the on-chip bus standard for System-on-Chip (SoC) designs, despite its inherent low performance. Within the AMBA framework, the Advanced High-performance Bus (AHB) is utilized to connect analog and digital signal processors, alongside high-performance memory controllers. Conversely, the AMBA Advanced Peripheral Bus (APB) facilitates connections to peripherals such as UARTs. Both buses are interconnected via a bridge, known as the AHB2APB Bridge, presenting a challenging proposition for the evaluation of AMBA-based systems. AMBA bus protocol, enables communication between different functional blocks or Intellectual Properties (IP), our endeavor focuses on building high-performance SoC designs. By exploiting the reusability of IP across different buses and supporting multiprocessor unit development, we strive to bridge the communication gap between high-performance AHB and low-speed APB. The simulation of the AHB2APB Bridge module, designed in Verilog HDL is conducted on the Xilinx Vivado platform. Our primary objective is to achieve high-speed pipelined data transfers while ensuring no data loss during transmission Key Words: System on chip, AHB2APB, Verilog HDL, Xilinx Vivado

AHB Interconnect - Functional Verification

This paper offers an in-depth exploration of the verification procedure pertaining to the integration of an Advanced High-performance Bus (AHB) Interconnect module. The verification process holds pivotal significance within chip development, entailing thorough validation and examination of the hardware design before entering the mass production phase. The principal objective of this verification process is to meticulously unearth potential bugs or imperfections embedded in the design, which could potentially trigger undesirable outcomes, compromised performance, or even critical malfunctions in the final product. At the heart of this verification approach lies the functional verification paradigm, centered around simulation-based testing. Within this framework, the AHB Interconnect module is instantiated in a controlled verification environment designed to emulate real-world scenarios. This environment orchestrates input stimuli to the module and captures ensuing outputs generated by it. The environment is meticulously programmed to anticipate specific behavioral patterns from the module. Deviations from these anticipated behaviors are promptly flagged as errors. This meticulous methodology serves to guarantee that the module aligns with its intended operations and strictly adheres to predefined functional benchmarks. The paper is dedicated to Acad. Florin Gheorghe Filip, at his 15th anniversary as the Chairman of the Information Science and Technology Section of the Romanian Academy, and at his 75th anniversary.

Data Transaction using AHB Protocol

Data Transaction using AHB Protocol

An Easy-to-Integrate IP Design of AHB Slave Bus Interface for the Security Chip of IoT

Information security is fundamental to the Internet of things (IoT) devices, in which security chip is an important means. This paper proposes an Advanced High-performance Bus Slave Control IP (AHB-SIP), which applies to cryptographic accelerators in IoT security chips. Composed by four types of function registers and AHB Interface Control Logic (AICL), AHB-SIP has a simple and easy-to-use structure. The System on Chip (SoC) design can be realized by quickly converting the nonstandard interface of the security module to the AHB slave interface. AHB-SIP is applied to the security accelerators of SM2, SM3, and SM4 and random number generator (RNG). Combined with a low-power embedded CPU, TIMER, UART, SPI, IIC, and other communication interfaces, a configurable SoC can be integrated. Moreover, SMIC 110 nm technology is employed to tape out the SoC on a silicon chip. The area of AHB-SIP is 0.072 mm2, only occupying 6‰ of the chip (3.45 ∗ 3.45 mm2), and the power consumption of encryption modules combined with AHB-SIP is lower than that combined with AXI interface, which is decreased up to 61.0% and is ideal for the application of IoT.

Design of Advanced High Performance Bus Tracer in System on Chip Using Matrix Based Compression for Low Power Applications

This project proposes multilayer advanced high-performance bus architecture for low power applications. The proposed AHB architecture consists of the bus arbiter and the bus tracer (A.R.M.A., 1999. Specification (Rev 2.0) ARM IHI0011A). The bus arbiter, which is self motivated selects the input packet based on the control signals of the incoming packet. So that arbitration leads to a maximum performance. The On-Chip bus is an important system-on-chip infrastructure that connects major hardware components. Monitoring the on-chip bus signals is crucial to the SoC debugging and performance analysis/optimization (Gu, R.T., et al., 2007. A Low Cost Tile-Based 3D Graphics Full Pipeline with Real-Time Performance Monitoring Support for OpenGL ES in Consumer Electronics. 2007 IEEE International Symposium on Consumer Electronics, June; IEEE. pp.1–6). But, such signals are difficult to observe since they are deeply embedded in a SoC and there are often no sufficient I/O pins to access these signals. Therefore, a straightforward approach is to embed a bus tracer in SoC to capture the bus signal trace and store the trace in on-chip storage such as the trace memory which could then be off loaded to outside world for analysis. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built in compression mechanisms such as dictionary based compression scheme for address and control signals and differential compression scheme for data. To improve the compression ratio matrix based compression which is lossless compression is used instead of differential compression. This system is designed using Verilog HDL, simulated using Modelsim and synthesized using Xilinx software.

Modified Encryption Standard with High Performance through Secure Protocol

The Advanced Encryption Standard (AES) has been accepted worldwide as a desirable algorithm to encryption and decryption sensitive information. In cryptography the unencrypted information referrers to as plaintext it is encrypted into cipher-text, which will in turn be decrypted back into the usable plaintext. The encryption and decryption are based on the type of cryptography system and secret keys. The secret key is responsible for preparing the input key to be used by the cipher in each round. AES with one-stage pipeline producing minor reduction of delay but does not show any improvement in area and power consumption. To overcome the above drawbacks, the basic architecture of AES, which includes encryption and decryption can be modified with one stage pipeline architecture by using one- dimensional Substitute Box (SBOX). Advanced Microcontroller Bus Architecture (AMBA) describes level of an on-chip communication standards for elevated performance embedded microcontrollers. AMBA AHB (Advanced High Performance Bus) is intended for elevated performance and high-frequency clocks. AHB has unique characteristics such as burst transfer, split transaction and single-cycle master bus transfer. 128 bit plain text is guided by AMBA-AHB requirements and can be used to send a plain text block to the cypher per clock cycle.. Plain text of 128 bit is driven by AMBA-Advanced High-performance Bus. AMBA-AHB specifications and supports the transmission to the cipher of a plain text block per clock cycle i.e., Modified Encryption Standard will be implemented with AMBA –AHB driven by input, which provides on-chip communication, increasing security of encryption standard. Propositioning methodology, Modified Encryption Standard will be simulated and synthesized by using Xilinx ISim 14.7 FPGA.

Design and Verification of Advanced High-Performance Bus Lite Protocol Using Questa Sim

Design and Verification of Advanced High-Performance Bus Lite Protocol Using Questa Sim

Design and Implementation of a Direct Memory Access Controller for Embedded Applications

In this paper, we propose a design and implementation of a Direct Memory Access Controller (DMAC) as a part of an SoC. The main purpose of the DMAC design is to integrate it into a System on a Chip (SoC) for the exchange of a large volume of data between the memory and peripherals at high speed. The proposed DMAC works on Advanced Microcontroller Bus Architecture (AMBA) specifications. Internally, these specifications define two buses, Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB). The Direct Memory Access (DMA) controller functions as the bridge between AHB and APB and allows them to work in parallel. It works either in buffer or non-buffer data transfer mode, according to the peripheral speed. This is synchronized with an asynchronous FIFO. Fast data reads can be achieved by using an AMBA based DMA controller with a processor in the SoC. This means that the DMAC provides a high volume of data transfer. Hence, the proposed DMAC is a better option for high volumes of data, as well as for timing. It can be concluded that if using this AMBA-based DMA controller the issues of high speed and high volume data have been resolved. Comparison is made with ARM processors, such as Cortex A8 and ZC702, and design comparison with Xilinx DMA is also made. The DMAC is viewed as a more appropriate choice.

VLSI Design of AMBA Based AHB2APB Bridge

The Advanced Microcontroller Bus Architecture (AMBA) is an open System-on-Chip bus protocol for highperformance buses to communicate with low-power devices. In the AMBA Advanced High Performance bus (AHB) a system bus is used to connect a processor, a DSP, and high-performance memory controllers where as the AMBA Advanced Peripheral Bus (APB) is used to connect (Universal Asynchronous Receiver Transmitter) UART. It also contains a Bridge, which connects the AHB and APB buses. Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way. So AHB2APB bridge is designed, implemented using VERILOG tool and tested using Verilog testbench and is reported in this paper. A synthesizable RTL code of a complex interface bridge between AHB and APB is developed and known as AHB2APB Bridge. The simulated AHB2APB Bridge results are promising and can be further tested for its verstality by writing a verification program using UVM in future.

VLSI Design of AMBA Based AHB2APB Bridge

The Advanced Microcontroller Bus Architecture (AMBA) is an open System-on-Chip bus protocol for highperformance buses to communicate with low-power devices. In the AMBA Advanced High Performance bus (AHB) a system bus is used to connect a processor, a DSP, and high-performance memory controllers where as the AMBA Advanced Peripheral Bus (APB) is used to connect (Universal Asynchronous Receiver Transmitter) UART. It also contains a Bridge, which connects the AHB and APB buses. Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way. So AHB2APB bridge is designed, implemented using VERILOG tool and tested using Verilog testbench and is reported in this paper. A synthesizable RTL code of a complex interface bridge between AHB and APB is developed and known as AHB2APB Bridge. The simulated AHB2APB Bridge results are promising and can be further tested for its verstality by writing a verification program using UVM in future.

Monitoring and Control Platform for Homes Based on FPGA, SoC and Web Technologies

With the development of mobile and internet technologies, the interest in home automation has grown over the past years. This paper shows an implementation of a monitoring and control platform for homes based on FPGA (Field Programmable Gate Arrays) structures, embedded systems and web technologies, which is different from other existing approaches. In the end, the current implementation provides a template model which gives a user the possibility to adapt existing devices and appliances, commonly found in houses, to the platform with minor changes. It also allows the control of multiple houses over the internet from one single web page. The system's main component which controls all the physical devices consists of an embedded system based on ARM Cortex M0 IP Core and AHB-Lite (Advanced High-performance Bus - Lite) protocol.

FPGA Implementation of AHB to APB Protocol

The field of technology is evolving at a very fast pace. The competition is very intense. So the need of the hour is to produce efficient system. In accomplishing this objective we are required to establish better interaction among all the components of the system. This requirement is fulfilled by the Advanced Microcontroller Bus Architecture (AMBA) protocol from Advanced RISC Machines (ARM).The AMBA is the on-chip standard for the communication among components in Application Specific Integrated Circuits (ASIC) or System on Chip (SoC). This paper focuses on the 2 protocols of AMBA which are Advanced High Performance Bus (AHB) and Advanced Peripheral Bus (APB) and the APB bridge. The coding is done in Verilog synthesis on Xilinx 14.7 ISE and simulation on ISim simulator and FPGA implementation on Spartan 3.

Implementation of AMBA AHB protocol using verilog HDL

Advanced Microcontroller Bus Architecture (AMBA) is a series of bus protocols provided by ARM. These include AHB, APB and ASB. AMBA provides an on-chip communication standard for these buses to be used in high performance microcontrollers. In this paper we have implemented the AMBA AHB (Advanced High-Performance Bus) which is used for high performance transfers among different modules of the microcontroller. AHB supports efficient connection of processor, on chip memory, DMA and off chip external memories. AMBA AHB system bus supports multiple bus masters and slaves. The design is implemented using Verilog HDL and simulated using ModelSim 6.4a. Synthesis for the design is done using Xilinx ISE 14.4.

A novel bus transfer mode (AS transfer) and a performance evaluation methodology

This paper proposes an innovative on-Chip bus transfer mode – the Advanced Encryption Standard (AES) state transfer (AS) and a performance evaluation methodology to estimate the transfer performance. By modeling and collecting several performance metrics including bus latency, bandwidth, valid bandwidth, power and energy consumption using the methodology, it enhances fidelity of the performance analysis and evaluation. As a case study, we formally complete the hardware implementation flow on Advanced High-Performance Bus (AHB), Advanced eXensible Interface 4 (AXI4) and AS bus (ASBUS) DMA, and demonstrate high estimation accuracy by comparing all the experimental results. Both static analysis and hardware implementation results show that the data transfer latency is close to 29% of AHB and 58% of AXI4 by using the AS transfer. Moreover, it is observed that this high-efficiency transfer mode of ASBUS helps to enhance the valid data bandwidth to around 3.4 times that of AHB and 1.7 times that of AXI4, and the energy consumption of ASBUS is only a half of AHB and AXI4. Furthermore, the proposed evaluation methodology is effectively used with sufficient accuracy (the average estimation error: 3.3%) in the design flow.

A High-Performance On-Chip Bus (MSBUS) Design and Verification

This brief proposes a high-performance system-on-chip bus protocol termed the master-slave bus (MSBUS). Considering the inevitable tradeoff among area, throughput and energy efficiency, the control bus is developed as a low-cost and low-power bus, and the data bus is created as a high-throughput full-duplex bus with the feature of block data transfer. To evaluate the bus performance, we create four analytical models including transfer time consumption (TC), wire efficiency (WE), valid data bandwidth (VDB) and dynamic energy efficiency. Then, the advanced high-performance bus-, advanced eXensible interface (AXI)-, and MSBUS-based direct memory access (DMA) are developed as a case study of hardware implementation. It is observed that MSBUS DMA costs less hardware resources and achieves higher performance, especially in the block transfer mode. For instance, the results from both the analytical models and the practical tests show that the TC of MSBUS is close to 63% of the AXI, the WE and VDB of MSBUS are almost 2.3 and 1.6 times of the AXI respectively, and the energy consumption is half of AXI in the block transfer mode.

English

This paper gives a brief description of various on-chip bus protocols such as the Advanced Microcontroller Bus Architecture (AMBA) Advanced High-Performance bus (AHB) and Advanced Extensible Interface (AXI), Wishbone Bus, Open Core Protocol (OCP) and CoreConnect Bus. It gives a brief introduction of high performance system-on-chip bus protocol termed as the master-slave bus (MSBUS). By taking into consideration the inevitable trade-off among area, throughput and energy efficiency, the control bus is developed as low-cost and lowpower bus whereas the data bus is created as a high-throughput full-duplex bus. This on-chip bus protocol is differentiated from other on-chip bus protocols with feature of efficient block data transfer. This MSBUS is an effective bus protocol in many applications such as image processing, computer vision, and wireless communication where it requires less hardware resources and achieves higher performance, especially in block transfer mode. The comparison is made between different protocols with respect to various parameters.

An AMBA Advanced High performance Bus Tracer with Real time Compression for Support of SoC

AMBA (Advanced Microcontroller based Bus Architecture) consists of AHB (Advanced High performance Bus), APB (Advanced Peripheral Bus), ASB (Advanced System Bus) and AXI (Advanced extensible Bus). This Paper proposes the debugging and analyses of system on chip (SoC) at various test conditions by verifying the functional aspects of the on-chip bus. Here we select an Advanced High performance bus (AHB), since the AHB bus signals are hard to examine as they are extremely embedded in the system on chip and there are no sufficient I/O pins to access these signals. Hence we embed a bus tracer in SoC to capture and compress the bus signals with different compression mechanisms. The tracer is successfully verified in FPGA SPARTAN 3E (XC3S500E). Tools used in this manuscript Modelsim for simulation and XILINX ISE II for RTL Synthesis.

Assertion based functional verification analysis of AMBA-AHB using System Verilog

A widely used advanced microprocessor bus architecture (AMBA) aims at easing the component design by using the combination of interchangeable components in the system-on-chip (SoC) designs (ARM Ltd., 1999). This paper presents the implementation and functional verification of widely used advanced high-performance bus (AHB) protocol of AMBA using assertion based functional verification approach. This paper contributes as follows: 1) implementation of AMBA-AHB protocol using System Verilog language in Synopsys VCS® tool; 2) assertions implementation for different components of the design; 3) functional verification of the overall design using assertions and analysis of the obtained coverage report from Synopsys VCS®. All the assertions and coverage analysis results are combined together to get the overall functional coverage of the AMBA-AHB design. The final functional coverage of the design comes out to be 97.42%. The main aim of this work is to implement AMBA-AHB protocol using System Verilog and analyse the coverage reports of different types of coverages reported by Synopsys VCS®. The result of the analysis is shown in different types of coverages to verify the completeness of the design by observing the shortcomings in the testbench and improving them for enhancing the overall functional coverage using System Verilog in Synopsys VCS®.

An AHB on Chip Bus Tracer with Real Time Compression for SoC Support

This paper illustrates the system on chip (SoC) debugging and analyses its behavior at several test conditions by verifying the functional aspects of the on-chip bus. Here an Advanced High performance bus (AHB) is selected, since the AHB bus signals are difficult to observe as they are deeply embedded in the system on chip and these I/O pins to access these signals is not possible. Hence we embed a bus tracer in SoC to capture and compress the bus signals. The tracer is successfully verified in FPGA. In this manuscript the selected software is XILINX ISE software design environment for RTL synthesis and model-Sim simulation software to verify the timing diagrams of the AHB SoC modules designed. The FPGA used is SPARTAN 3E (XC3S500E).