Advanced Encryption Standard Hardware Research Articles

Low area and high throughput implementation of advanced encryption standard hardware accelerator on FPGA using Mux‐Demux pair

AbstractNow‐a‐days advanced cryptographic algorithms are needed in order to improve data security and confidentiality. One such algorithm used prominently is advanced encryption standard (AES) algorithm. AES is a complex algorithm with multiple rounds of processing data and occupies more space or area when implemented on hardware. Since each sub‐step of computation has a similar structure, the proposed method employs the novel idea of using the same hardware to implement the AES functionality. Hence the number of logical units occupied are leveraged. The proposed scheme, Mux‐Demux pair method (MDP), uses a mux‐demux structure. It is implemented on Virtex‐7 and ZynQ7000 FPGAs and the code is written in Verilog HDL language in the Vivado software. The proposed work when simulated on Virtex‐7 occupies an area of 1932 slices, giving an optimized throughput of 10.167 Gbps while the work simulated on ZynQ7000 occupies an area of 3253 slices, resulting in a throughput of 23.858 Gbps.

Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array‐A survey

AbstractWith the majority of users migrating to a cloud computing platform, the responsibility for data security has increased considerably. As data with various levels of sensitivity moves out of the confines of the system firewall, there is no control over where it resides; it depends on the cloud server being used. This makes the use of secured cryptographic algorithms necessary to improve data security and maintain the confidentiality of data. The encryption algorithm used most extensively today is the Advanced Encryption Standard (AES). Hardware acceleration with Field Programmable Gate Array can improve the performance of AES. This study examines various approaches for improving data encryption methods that can be utilized as hardware accelerators to improve the fundamental AES cipher. Some research publications suggest ways to boost throughput while others advise ways to save area and power. Many subsequent developments have also used other cryptographic methods such as RSA and ECC to improve key management security. This study examines the outcomes of multiple ways for metrics including throughput, area, power, and data security, and explains some of the best implementation solutions for each metric individually.

Reliable advanced encryption standard hardware implementation: 32- bit and 64-bit data-paths

Cryptographic primitives are extensively used in today's applications to provide the desired security. Malicious or accidental faults that occur in the hardware implementations of cryptographic primitives, specifically in this paper the Advanced Encryption Standard (AES), can result in an erroneous output of encryption/decryption process and reduce the reliability of the cryptographic hardware. The use of a suitable fault-tolerant scheme for AES, to recover it from failures or attacks and bring it back to an operational state, is crucial for reliability, and consequently for security purposes. In this paper, two novel online fault-tolerant schemes are proposed for AES. In the proposed fault-tolerant architecture, the round path is modified and divided it into two pipeline stages. The proposed fault-tolerant schemes are based on a combination of hardware and time redundancies, where a new hardware redundancy is proposed for the AES round function and a time redundancy for the hardware of the AES key expansion unit. The presented fault-tolerant schemes are valid for all versions of AES and are independent of its S-box implementation manner. Both ASIC and FPGA implementations of the original and the proposed fault-tolerant AES along with Full TMR (Triple Modular Redundancy) and Full TTR (Triple Time Redundancy) structures are reported as traditional fault-tolerant schemes. It is shown that the first proposed fault-tolerant architecture, named TMRrp&TTRke32, outperforms these approaches and the previous report in the literature in terms of area overhead and therefore power consumption. Also, the other approach, named TMRrp&TTRke64, is better than the other approaches in achieving a trade-off between area overhead and throughput overhead.

Performance Evaluation of Lightweight Advanced Encryption Standard Hardware Implementation

Advanced Encryption Standard (AES) is one of the most secured encryption algorithm because of its robustness and complexity. Because of its complexity, AES has slow computation. This paper presents a Lightweight Advanced Encryption Standard (LAES) design by replacing the MixColumn transformation of the traditional AES with a 128-bit permutation to lessen its computational complexity. Implementation of hardware cryptographic encryption aims to find the best trade-off between throughput and resource utilization. The proposed design is synthesized on various Field Programmable Gate Array (FPGA) devices and achieves the maximum clock frequency of 480.50 MHz with the highest throughput of 6.15 Gbps when synthesized on Virtex 7 XC7VX690T. The results on other devices show a higher throughput, better performance efficiency, and lesser area utilization when compared to the existing AES hardware implementation.

Low‐power secure S‐box circuit using charge‐sharing symmetric adiabatic logic for advanced encryption standard hardware design

The previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit is implemented in this paper using a multi-stage positive polarity Reed–Muller representation with a composite field technique. The CSSAL and other conventional dual-rail adiabatic logics are evaluated from the view point of the transitional power fluctuation and the peak current traces in the 8-bit S-box in order to compare their resistance against side-channel attacks. A method to eliminate unwanted glitch current, the triple power clock supplies are applied to each inversion block; thus, the CSSAL S-box circuit performs uniform peak current traces and it has significant power reduction, which is applicable for high security demand and low power devices, such as smart cards, radio frequency identity tags or wireless sensors. The results are obtained from the SPICE simulation with a 0.18-μm 1.8-V standard complementary metal–oxide semiconductor technology at an operating frequency band of 1.25 KHz–70 MHz.

Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance

This work presents the design, hardware implementation, and performance analysis of novel asynchronous AES (advanced encryption standard) Key Expander and Round Function, which offer increased side-channel attack (SCA) resistance. These designs are based on a delay-insensitive (DI) logic paradigm known as null convention logic (NCL), which supports useful properties for resisting SCAs including dual-rail encoding, clock-free operation, and monotonic transitions. Potential benefits include reduced and more uniform switching activities and reduced signal-to-noise (SNR) ratio. A novel method to further augment NCL AES hardware with random voltage scaling technique is also presented for additional security. Thereby, the proposed components leak significantly less side-channel information than conventional clocked approaches. To quantitatively verify such improvements, functional verification and WASSO (weighted average simultaneous switching output) analysis have been carried out on both conventional synchronous approach and the proposed NCL based approach using Mentor Graphics ModelSim and Xilinx simulation tools. Hardware implementation has been carried out on both designs exploiting a specified side-channel attack standard evaluation FPGA board, called SASEBO-GII, and the corresponding power waveforms for both designs have been collected. Along with the results of software simulations, we have analyzed the collected waveforms to validate the claims related to benefits of the proposed cryptohardware design approach.

Secure Testable S-box Architecture for Cryptographic Hardware Implementation

It has been recently shown that observability of design for testability techniques compromises cryptographic hardware implementation security in a straightforward manner. During test, the chip can be configured so that it is possible to observe temporal data resulting from the encryption process of a plaintext that eventually exposes the secret key. To this end, we propose a C-testable S-box implementation which is one of the most complex blocks in advanced encryption standard hardware implementation. We divide the S-box structure into a positive polarity Reed–Muller form and tested independently using a BIST circuit. The proposed structure does not use any scan chain for testability, hence avoiding the vulnerability of the chip during testing. Only 14 constant vectors are sufficient to achieve 100% fault coverage in the S-box. The C-testable feature comes with an extra hardware overhead of 15 per cent. By introducing an on-chip testing feature one can avoid potential paths for introducing unwanted access into the on-chip security blocks.