Advanced Encryption Standard Decryption Research Articles

Data protection enhancement in smart grid communication: An efficient multi-layer encrypting approach based on chaotic techniques and steganography

In this study, a multi-layer encryption system is proposed through which sensitive and important data in smart grids can be secured from unauthorized persons as well as cyber threats. The suggested system is analyzed using fundamental performance assessment metrics say as average processing times across ten runs, peak signal-to-noise ratio (PSNR), and root mean square error (RMSE). The encryption process involves hiding the data encrypted by a digital dictionary and the advanced encryption standard (AES) algorithm in an image. In this way, AES encryption suggests rapid processing with a short average time per each block; similarly, the decryption technique, which includes the dictionary and AES decryption also renders the results in a justified computational time nominating it as a practical approach. It is worth noting that the small key era and dictionary construction instances provoke innovations in the general efficiency of the encryption mechanism. The conducted study, based on recorded values for PSNR, RMSE, UACI, and NPCR, demonstrates that the proposed multi-layer encryption system, which incorporates dictionary encryption and AES, is a robust and a fast method to shield important information and attaining a balance between protection and computational time.

Formal Approach for Verifying Galois Field Arithmetic Circuits of Higher Degrees

This paper presents an efficient approach to verifying higher-degree Galois-field (GF) arithmetic circuits. The proposed method describes GF arithmetic circuits using a mathematical graph-based representation and verifies them by a combination of algebraic transformations and a new verification method based on natural deduction for first-order predicate logic with equal sign. The natural deduction method can verify one type of higher-degree GF arithmetic circuit efficiently while the existing methods require an enormous amount of time, if they can verify them at all. In this paper, we first apply the proposed method to the design and verification of various Reed-Solomon (RS) code decoders. We confirm that the proposed method can verify RS decoders with higher-degree functions while the existing method needs a lot of time or fail. In particular, we show that the proposed method can be applied to practical decoders with 8-bit symbols, which are performed with up to 2,040-bit operands. We then demonstrate the design and verification of the Advanced Encryption Standard (AES) encryption and decryption processors. As a result, the proposed method successfully verifies the AES decryption datapath while an existing method fails.

A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl

This article describes the design of a compact 8-bit coprocessor for the Advanced Encryption standard (AES) (encryption, decryption, and key expansion) and the cryptographic hash function Grøstl. Our Arithmetic and Logic Unit has only one instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and Grøstl at all levels of security (i.e. 128-, 192-, and 256-bit encryption keys; 256- and 512-bit message digests). A fully autonomous implementation of Grøstl and AES on a Virtex-6 FPGA requires 169 slices and a single 36k memory block, and achieves a competitive throughput (up to 217 Mbits/s and 92 Mbits/s for encryption and hashing, respectively). The proposed coprocessor is well-suited for resource-constrained embedded systems, where several security protocols rely only on block ciphers and hash functions. One can exploit the design philosophy presented in this paper in order to design a unified architecture for other algorithms.

Design and Implementation of Enhanced Affine and Inverse Affine Transformation Based Composite S-box for AES Encryption and Decryption

The Substitution Box (S-Box) and Inverse MixColumn (Inv MixColumn) forms core building blocks in Advanced Encryption Standard (AES) based Security Algorithm. This study presents full custom design of Composite S-Box by reducing the composite field arithmetic of Multiplication Inverse (MI) and Affine/Inverse Affine Transformation. Design of proposed new MI and Affine/Inverse Affine Transformation techniques are integrated in Composite S-Box of both AES Encryption and Decryption. Very Large Scale Integration (VLSI) System design environment is considered in this research work to measure the performance improvement. High Speed, less area utilization and Lower power consumptions are the important parameter in VLSI System design environment. Hence, the main goal of this research work is to reduce the hardware complexity, Power and Delay consumption of AES Encryption and Decryption process. The principle of reducing the redundant functions is used in both MI and Affine/Inverse Affine Transformation of Proposed Composite S-Box design for reducing the hardware complexity and power consumption. Proposed new Composite S-Box design offers 6.52% reduction of Slices, 5.68% reduction of Look up Tables (LUTs), 2.24% reduction of delay and 6.15% reduction of Power consumption than traditional Composite S-Box design. Further Proposed new composite S-Box design is integrated into both AES encryption and AES decryption process to improve the performance evaluation of AES algorithm.

FPGA Implementation of Hiding Information using Cryptography

Background: The main threat in communication is the unauthorized access of information third party without the knowledge of sender and receiver. Hence the security plays a vital role in data transmission systems. Confidential data like internet banking account passwords and email account passwords needs security in their text data. Data can be text, image, video and audio. Methods: The purpose of this research work is to implement a mechanism to hide information (image) using cryptography. Advanced Encryption Standard (AES) is a type of symmetric cryptography standard which can be used to transfer a block of information securely during transmission. Findings: The idea of this paper is to generate an encrypted image by giving image input to AES encryption system and getting the decrypted image as original image by giving encrypted image as input to the AES decryption system. The input image is given through MATLAB R2012b to ModelSim6.3 and the system simulation and synthesis is done by integrating Model Sim to the Altera DE2 115 board through Quartus II software. Conclusion: The maximum frequency attained from this workis 165.462MHz. Finally image is displayed through an LCD which is connected to the board using Video Graphics Array (VGA) Connector.

Design of AES Pipelined Architecture for Image Encryption/Decryption Module

The relentless growth of Internet and communication technologies has made the extensive use of images unavoidable. The specific characteristics of image like high transmission rate with limited bandwidth, redundancy, bulk capacity and correlation among pixels makes standard algorithms not suitable for image encryption. In order to overcome these limitations for real time applications, design of new algorithms that require less computational power while preserving a sufficient level of security has always been a subject of interest. Here Advanced Encryption Standard (AES),as the most widely used encryption algorithm in many security applications. AES standard has different key size variants, where longer bit keys provide more secure ciphered text output. The available AES algorithm is used for data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to Pipelined AES algorithm through Textio, to obtain the encrypted image. and the encrypted image is the input to Pipelined AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit Pipelined AES algorithm for image encryption and decryption, also to compare the latency , efficiency, security, frequency & throughput . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language.

A Novel Biometric Cryptosystem using LDPC and SHA based Iris Recognition

We use Low Density Parity Check (LDPC) error correction code to solve fuzziness i.e., the variability and noise in iris code generated from Iris Recognition System (IRS) and Secure Hash Algorithm (SHA-512) to transform unique iris code into hash string to make them as a Cancellable Biometric. SHA-512 hash string is used as a key for 512 bits Advanced Encryption Standard (AES) encryption process. In the decryption process, Hash comparison is made between new hash generated by SHA-512 from error corrected iris code and hash stored in smart card. If authentic, 512 bits AES decryption is accomplished. Experiments indicate that, use of LDPC code results in better separation between genuine and impostor users which improves the performance of this novel cryptosystem. Security of this system is very high, which is 2 under birthday attack. AES algorithm is enhanced by using 512 bits key and increasing the number of rounds. General Terms Iris Pattern Recognition, Cryptography, Computer Security.