Advanced BiCMOS Research Articles

Analysis and Comparison of High-Resolution GS/s Samplers in Advanced BiCMOS and CMOS

High-speed and high-resolution analog to digital converters (ADCs) (10+ bits) are essential components of modern wireless communication systems and mmWave radios. Their performance is often limited by the noise and distortion from the front-end samplers, the design of which can be challenging. Modern ADC design has moved heavily to scaled CMOS technologies due to its attractive digital and integration capabilities, but these processes face challenges of high fabrication costs, and diminishing analog performance that has to be bolstered by extensive digital calibration. On the other hand, BiCMOS processes have advanced and scaled sufficiently that they may be able to offer the best of the mixed signal world. This brief examines, both theoretically and through simulations, the design of samplers for high-speed, low-distortion in CMOS and BiCMOS for GS/s ADCs. Two fully differential samplers, with an equivalent sampling frequency of 5 GS/s and an input frequency range of up to 10 GHz, are designed in a 90-nm BiCMOS and a 28-nm CMOS process, respectively, and their distortion performance is analyzed, simulated, and compared.

On the Challenges of SiGe HBTs in Advanced BiCMOS Technology Toward Half THz fMAX

Advanced BiCMOS technology is a cost-effective candidate for wide-range of applications, including Radar (automotive radars, high-speed industrial sensors), high-speed wireless and wireline communication, high-speed instrumentation, and mmWave THz imaging and sensing that require high performance SiGe HBTs with high cut-off frequencies fT and high maximum frequencies fMAX. Development of SiGe HBTs in BiCMOS technology with both high fT and fMAX faces significant challenges. Vertical scaling is employed to increase fT in advanced SiGe HBTs including reduction in base and collector thickness or by increasing the collector doping. All these approaches reduce the carrier transit times, but result in an increase in the base resistance and the collector-base capacitance, which degrade fMAX. To overcome these limits, lateral scaling is necessary to reduce the base resistance and the collector-base capacitance. Reduction in emitter width reduces the intrinsic base resistance and Ccb, self-aligned emitter-base integration schemes reduce the extrinsic base link resistance, and raised extrinsic base helps with lower Rb and Ccb. In short, these scaling rules and approaches would need to reduce both base resistance and collector-base capacitance simultaneously for improved fMAX and fT In this paper, results from two experimental studies are presented in a 90nm SiGe BiCMOS technology. Compared with the baseline, one experiment shows more reduction in collector-base capacitance, while the other shows more reduction in base resistance. Both experiments achieved 300GHz fT and met or exceeded the 360GHz fMAX goal of the technology. In addition to straight vertical and lateral scaling, a series of experiments employing other process techniques and structure innovation have also been studied and are reviewed in this paper, including millisecond anneal techniques, low temperature silicide and low temperature contact processes, and secondary trench isolation, achieving fT around 300GHz and fMAX toward half THz.

On the Challenges of SiGe HBTs in Advanced BiCMOS Technology Toward Half THz fMAX

Advanced BiCMOS technology employing SiGe HBTs is a cost-effective candidate for a wide range of exciting applications including automotive radar and 5G wireless communications. In this paper, results from two experimental studies are presented in an advanced 90nm SiGe BiCMOS technology in production. One experiment reduces the collector-base capacitance, while the other reduces base resistance. Both experiments achieved 300GHz fT and met or exceeded the 360GHz fMAX goal of the technology. Furthermore, results from a series of experiments are also reviewed in this paper, showing paths toward SiGe HBTs of half THz fMAX and fT around 300 GHz, based on the same 90nm SiGe BiCMOS technology.

Millimeter-wave miniaturized hybrid couplers integrated on advanced bicmos technology

In this article, we present the design and the measurement of two hybrid couplers for millimeter-wave applications realized in the BiCMOS9MW 130nm process (ST Microelectronics). The aim is to demonstrate several miniaturization possibilities of a conventional branchline coupler while maintaining a constant 90° phase shift and a low insertion loss over the full 57–66-GHz band. The first miniaturized coupler is composed of meandered transmission lines; the second is a quasi-lumped quadrature coupler with discrete capacitors. The performance of these circuits is compared with the most recent on-chip 60-GHz couplers. We especially demonstrate the possibility to achieve state-of-the-art performance while using miniaturization techniques. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2221–2223, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27079

CMOS reliability issues for emerging cryogenic Lunar electronics applications

We investigate the reliability issues associated with the application of CMOS devices contained within an advanced SiGe HBT BiCMOS technology to emerging cryogenic space electronics (e.g., down to 43 K, for Lunar missions). Reduced temperature operation improves CMOS device performance (e.g., transconductance, carrier mobility, subthreshold swing, and output current drive), as expected. However, operation at cryogenic temperatures also causes serious device reliability concerns, since it aggravates hot-carrier effects, effectively decreasing the inferred device lifetime significantly, especially at short gate lengths. In the paper, hot-carrier effects are demonstrated to be a stronger function of the device gate length than the temperature, suggesting that significant trade-offs between the gate length and the operational temperature must be made in order to ensure safe and reliable operation over typical projected mission lifetimes in these hostile environments.

Epitaxial Realignment of In-Situ Doped Polycrystalline Silicon for Advanced BiCMOS Technologies

AbstractIndustrial feasibility of an in-situ-doped (ISD) polycrystalline Si process using chemical vapor deposition for advanced BiCMOS technologies is presented. ISD As-doped amorphous and polycrystalline Si layers have been deposited on Si substrates at 610°C and 660°C, respectively, with the deposition rate varying from 120 to 128Å /minute. Samples are compared on the basis of having been subjected to a substrate preclean prior to deposition using an HF solution and an in-situ H2 bake. TEM micrographs reveal the presence of a thin (10-15 Å) native oxide at the deposited layer/substrate interface for samples not precleaned. This is confirmed for both the amorphous and polycrystalline Si depositions. However, for the 610°C-deposited samples given the substrate preclean, a polycrystalline structure with partial epitaxial layer growth is observed. Twins and stacking faults are found at the poly Si/single crystal Si interface, causing interfacial roughness. Post-deposition annealing of the Si films typically generates grain growth, but RBS-channeling characterization of the annealed Si provides evidence of some recrystallization, the extent of which is affected by the original growth condition. Analysis shows that the amorphous deposition at 610°C results in a mixture of epitaxial and polycrystalline Si. Epitaxial realignment of the polycrystalline Si film by post deposition annealing can result in significantly improved device performance.

Measurement method for accurate extraction of the base-to-emitter intrinsic and peripheral capacitances of bipolar transistors

A simple measurement method to determine the intrinsic and peripheral emitter junction capacitances is described. The method is based on measurements of BJT's with different emitter geometries and is demonstrated on transistors of an advanced BiCMOS technology. The method can be applied directly to standard deep-submicrometer devices. No special test devices are required. By determining peripheral capacitance for different processes, the method enables the examination of process schemes designed to suppress the effect of the peripheral emitter on the transistor action. The method also provides a useful approach to monitor the scaling behavior of the intrinsic and peripheral capacitances. Results indicate the peripheral capacitance starts dominating the total capacitance as the emitter is scaled into the submicrometer range. For devices with quarter micron emitter widths, the peripheral capacitance is found to be 3 to 4 times higher than the intrinsic capacitance, and puts a fundamental limitation on device design. >

A 5 V, 6-b, 80 Ms/s BiCMOS flash ADC

A 5 V single supply, 6-bit flash A/D converter (ADC) has been developed that supports sampling rates of up to 80 Ms/s. The converter is optimized to operate in undersampling applications where the ADC has to deliver greater than 5.2 Effective Number Of Bits (ENOB's) with input frequencies well beyond Nyquist. Excellent dynamic linearity performance has been achieved with input frequencies up to 75 MHz and a gain flatness of better than 0.1 dB is obtained over the input signal spectrum of 50 MHz-95 MHz. This ADC is fabricated on a 1.0 /spl mu/m advanced BiCMOS process that features trench-isolated bipolar devices with an f/sub t/ of 10 GHz. >

A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications

A single-poly, 0.8- mu m advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process described has been developed for high-performance application-specific IC (ASIC) applications with emphasis on embedded CMOS, BiCMOS, or emitter-coupled logic (ECL) memory as well as BiCMOS and ECL gate arrays and standard cells. The key features of this BiCMOS process are twin buried layers, low encroachment recessed oxide isolation, a double-diffused bipolar process, a single-poly architecture with silicided local interconnection, and four levels of metallization with tungsten plugs. Ring-oscillator gate delays of about 125 ps for BiCMOS, less than 90 ps for CMOS, and about 48 ps for ECL were obtained with this process. >

Characteristics of impact-ionization current in the advanced self-aligned polysilicon-emitter bipolar transistor

Using an algorithm to calculate the base current increase due to local thermal effects, the authors show that one can accurately measure the impact ionization current over the full range of collector current. From the measured impact ionization ratio, it was possible to quantitatively describe the characteristics of the space-charge modulation and base push-out effect over a wide range of collector current. Computer simulation results support the measured data. It is also shown that one can use the measured impact ionization ratio to distinguish small collector concentration variations and thickness differences. The characterization was performed for self-aligned polysilicon-emitter transistors in an advanced BiCMOS technology. >