Adiabatic Quantum-flux-parametron Research Articles

Adiabatic quantum-flux-parametron boosters for long interconnection and large fanouts

Adiabatic quantum flux parametron (AQFP) is energy-efficient superconducting logic that operates with zero static energy consumption and extremely small dynamic energy consumption thanks to the adiabatic switching of the logic gates. One drawback in AQFP logic circuits is the wire length and fan-out limitations because of the low driving ability of the logic gates, which results in a large circuit area and significant latency. In the present study, we propose AQFP boosters with high driving ability. Two types of AQFP boosters are proposed: one is composed of a parallel connection of AQFP buffers, and the other uses multistage buffers driven by one excitation clock. We evaluated the maximum wire length of the proposed boosters by circuit simulations, including thermal noises, and found that the maximum wire length is 3.9 mm for fan-out one and 1 mm for fan-out four. We implemented the boosters and demonstrated their correct operations at low-speed tests. We also demonstrated a 5-to-31 decoder using the proposed boosters. It was shown that the circuit area, latency, and energy consumption were improved by about 30% compared to the design without the boosters.

An Adiabatic Quantum-Flux-Parametron 8-bit Ripple Carry Adder Using Delay-Line Clocking

Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family that can operate with low switching energy due to adiabatic switching. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current. We demonstrated several AQFP logic gates with delay-line clocking and demonstrated a phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. In the present study, we design and demonstrate an AQFP 8-bit ripple carry adder with delay-line clocking to show that delay-line clocking and the phase skipping operation are applicable to large-scale AQFP circuits. The latency of this adder is 960 ps, which is 40% of that for a conventional design. Moreover, due to the phase skipping operation, the junction count is reduced to approximately 70% of that for the conventional design. We find that this adder can operate at up to 4 GHz. The above results indicate that large-scale AQFP circuits can operate with low latency and low junction count by using delay-line clocking and a phase skipping operation.

Design and Simulation of Phase Synchronizer for Adiabatic Quantum Flux Parametron Circuits

An adiabatic quantum flux parametron (AQFP) is a two-terminal superconducting device capable of amplifying or inverting digital input signals at near-kT energy dissipation. This ultra-low power device is desirable for myriad reasons, including high performance accelerator applications as CMOS processors become more and more limited by energy consumption. Promising performance results have been realized on AQFP processors; however, scaling these results to larger computing systems faces engineering challenges due to device density and power distribution. AQFP circuits require a multi-phase activation signal to propagate logic. If data is not properly aligned with the activation phase, it can be dropped or shifted to an incorrect phase and disrupt circuit operation. This work presents design and simulation of an activation phase synchronizer: a simple circuit that will accept data arriving on any phase and re-align it to a known phase of the subsequent cycle. The phase synchronizer can be useful for mitigating clock skew across clock domains or play an important role in asynchronous design where the arrival time of data may be unknown.

Adopting a Standard Track Routing Architecture for Next-Generation Hybrid AC/DC-Biased Logic Circuits

The adiabatic quantum-flux-parametron (AQFP) and rapid single flux quantum (RSFQ) logic families both provide distinct advantages for data processing using superconductor electronics. The development of next-generation AQFP-RSFQ hybrid logic circuits provides the opportunity to combine the benefits of both of these logic families. Adopting a standard track routing architecture for both AQFP and RSFQ layouts provides a unified framework for physical layout synthesis. We demonstrate a standard track routing architecture developed under the ColdFlux project and its implementation within AQFP. An additional advantage of the standard track routing architecture is that it provides a systematic way to overcome metal density requirements for modern-day fabrication processes. It also provides a methodical approach towards strategic moat placement for protection against unwanted flux trapping. Implementations of passive transmission line (PTL) connections and their physical placement for hybrid AQFP-RSFQ circuits are discussed. Several AQFP layouts for the ColdFlux project are redesigned to adopt the standard track routing architecture. Experimental simulation of moat performance is also presented.

A Full-Custom Design Flow and a Top-Down RTL-to-GDS Flow for Adiabatic Quantum-Flux-Parametron Logic Using a Commercial EDA Design Suite

The adiabatic quantum-flux-parametron (AQFP) circuit is a superconductor digital logic family with extremely low power consumption. It consumes five orders less power than the state-of-the-art CMOS circuits and three orders of magnitude less power than RSFQ circuits, another competing digital superconductor technology. The computing resources required by society are increasing every year, and the AQFP circuit is a strong candidate for the next generation of computers. In previous research, a 4-bit MANA microprocessor and a 16-bit Kogge-Stone adder using AQFP logic were designed and demonstrated. These circuits were designed almost by hand, and the development environment needs to be improved to implement AQFP circuits for practical applications. So, we used Synopsys EDA tools typically used for CMOS design to create a full-custom design flow for logic cell design and a top-down flow to design combinational logic circuits automatically. We integrated a circuit design editor with simulation and verification tools for the full-custom design flow. For the top-down flow, we created an environment that automatically performs logic synthesis, path balancing, cell placement, and signal and excitation routing. 1024-bit adders with more than two million Josephson junctions (JJs) have been successfully designed.

Demonstration of Interface Circuits for Adiabatic Quantum-Flux-Parametron Cell Library Using an Eight-Metal Layer Superconductor Process

In this paper, we designed and demonstrated interface circuits between AQFP (adiabatic quantum-flux-parametron) and RSFQ (rapid single-flux-quantum) circuits according to the established AQFP and RSFQ cell libraries using the MIT LL SFQ5ee process. The principles of these interfaces are based on ones that were previously designed and demonstrated using a four-metal-layer superconductor process. The AQFP-to-RSFQ interface is based on an RSFQ comparator, where an output current from an AQFP buffer is converted to an SFQ pulse output. The RSFQ-to-AQFP interface is based on an RSFQ D flip-flop, where the internal state of the D flip-flop is read out by an AQFP buffer. Thanks to the eight-metal-layer process, the interfaces can be designed with reduced circuit area compared to original designs with the four-metal-layer process. We designed, fabricated, and tested an AQFP-RSFQ hybrid multiplexer test circuit as an example of utilization of the interfaces, which results in correct operation with reasonably wide bias margins in low-frequency tests.

Design and Implementation of Energy-Efficient Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic

Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient, highperformance information processing systems. It has significantly low power dissipation thanks to the adiabatic switching of Josephson junctions. In this paper, we introduce an AQFPbased binary neural network (BNN) design methodology utilizing an in-memory computing scheme, analog accumulation, and a crossbar structure. The proposed design can effectively resolve the memory issue in superconducting digital circuits by significantly reducing memory usage in a non-Von Neumann fashion compared to conventional neural networks. As a proof-ofconcept, we designed and implemented an 8×8 AQFP BNN using the proposed design methodology targeted the AIST 10kA/cm2 4-layer niobium process. The Josephson junction count and energy dissipation of the proposed 8×8 BNN design are 2236 and 11.18 aJ, respectively.

Sigmoid function generator using stochastic adiabatic superconductor logic

Stochastic-computing-based artificial neural networks (SC-ANNs) can be used to perform hardware- and energy-efficient neuromorphic computing. We have been developing SC-ANNs using an energy-efficient superconductor logic family, namely, adiabatic quantum-flux-parametron (AQFP) logic. AQFP logic is suitable as a building block for SC-ANNs since it can perform stochastic operations with extremely small energy dissipation. In this Letter, we propose and demonstrate a sigmoid function generator (SFG) for AQFP SC-ANNs, which we refer to as the AQFP SFG. An SFG is an important circuit in neural networks that generates outputs from the sum of weighted inputs in accordance with the sigmoid function. The AQFP SFG performs the sigmoid function using a finite state machine based on an AQFP buffer coupled to a flux storage loop. We experimentally demonstrate that the AQFP SFG generates output signals from stochastic bitstreams in accordance with the sigmoid function and that the characteristics of the sigmoid function can be controlled by a bias current. Furthermore, we show that the AQFP SFG operates with small power dissipation due to its simple structure.

Scalability of Superconductor Electronics: Limitations Imposed by AC Clock and Flux Bias Transformers

Flux transformers are the necessary component of all superconductor digital integrated circuits utilizing ac power for logic cell excitation and clocking, and flux biasing, e.g., Adiabatic Quantum Flux Parametron (AQFP), Reciprocal Quantum Logic, superconducting sensor arrays, qubits, etc. We consider limitations to the integration scale (device number density) imposed by the critical current of the ac power transmission lines and cross coupling between the adjacent transformers. The former sets the minimum line width and the mutual coupling length in the transformer, whereas the latter sets the minimum spacing between the transformers. Decreasing linewidth of superconducting (Nb) wires increases kinetic inductance of the transformer's secondary, decreasing its length and mutual coupling to the primary. This limits the minimum size of transformers. As a result, there is a minimum linewidth ~100 nm which determines the maximum achievable scale of integration. Using AQFP circuits as an example, we calculate dependence of the AQFP number density on linewidth for various types of transformers and inductors available in the SFQ5ee fabrication process developed at MIT Lincoln Laboratory, and estimate the maximum circuit density as a few million AQFPs per cm^2. We propose an advanced fabrication process for a 10x increase in the density of AQFP and other ac-powered circuits. In this process, inductors are formed from a patterned bilayer of a geometrical inductance material (Nb) deposited over a layer of high kinetic inductance material (e.g., NbN). Individual pattering of the bilayer layers allows to create stripline inductors in a wide range of inductances, from the low values typical to Nb striplines to the high values typical for NbN thin films, and preserve sufficient mutual coupling in stripline transformers with extremely low crosstalk.

Scalable flux controllers using adiabatic superconductor logic for quantum processors

Quantum processors have the potential to accelerate specific computing tasks but are difficult to scale up due to engineering limitations, such as the number of available cables and cooling power for dilution refrigerators for quantum bits (qubits). Hence, it is very important to develop scalable, energy-efficient interface circuits that can control many qubits via a few control lines inside a dilution refrigerator. One of the most important interface circuits is the flux controller (FC), which generates arbitrary dc flux bias to adjust the characteristics of component devices such as qubits. In this paper, we propose and demonstrate FCs using an energy-efficient superconductor logic family, adiabatic quantum-flux-parametron (AQFP) logic. We develop two types of FCs: the AQFP FC and the AQFP/single-flux-quantum (AQFP/SFQ) FC. Both FCs require only a few control lines and have extremely small power dissipation, thus exhibiting high scalability. Furthermore, the AQFP/SFQ FC can control flux bias using ballistic SFQ transmission, which is crucial for integration with qubits. As a proof of concept, we demonstrate AQFP and AQFP/SFQ FCs at 4.2 K, fabricated by the AIST high-speed standard process. Our results indicate that AQFP logic is highly suitable for use as qubit interface circuits for very large-scale quantum processors, especially from the viewpoint of the control line count, power dissipation, and amount of supply currents.

Low clock skew superconductor adiabatic quantum-flux-parametron logic circuits based on grid-distributed blocks

Adiabatic quantum-flux-parametron (AQFP) is a promising superconductor logic family exhibiting extremely low switching energy. Traditional excitation of AQFP circuits depends on a pair of ac sources (i.e., four-phase clocking), whose currents are propagated throughout the chip to excite and clock each gate sequentially. This scheme, however, produces a considerably large clock skew due to the long propagation of the current pair and will heavily limit the scalability of an AQFP circuit. In this work, a global clocking scheme for low skew AQFP circuits is proposed based on microwave H-tree excitation networks and grid-distributed blocks. The H-tree network starts with a single transmission line (TL) but is exponentially split to several levels of TLs by using passive splitters, creating multiple leaves at the final level. A large-scale AQFP circuit can thus be distributed into several local blocks and clocked synchronously by the split currents from these leaves. Therefore, the accumulation of clock skew is limited to a small value only within each local block. For validation, a test circuit comprising four blocks with data interconnections between each other, and a 1-to-4 H-tree excitation network is demonstrated, where we obtain correct operation and wide excitation margins at gigahertz frequencies. The proposed clocking scheme is advantageous for the realization of very large-scale adiabatic superconductor logic circuits in the future.

Scalable true random number generator using adiabatic superconductor logic

Alternative computing such as stochastic computing and bio-inspired computing holds promise for overcoming the limitations of von Neumann computers. However, one difficulty in the implementation of such alternative computing is the need for a large number of random bits at the same time. To address this issue, we propose a scalable true-random-number generating scheme that we refer to as XORing shift registers (XSR). XSR generates multiple uncorrelated true random bitstreams using only two true random number generators as entropy sources and can thus be implemented by a variety of logic devices. Toward superconducting alternative computing, we implement XSR using an energy-efficient superconductor logic family, adiabatic quantum-flux-parametron (AQFP) logic. Furthermore, to demonstrate its performance, we design and observe an AQFP-based XSR circuit that generates four random bitstreams in parallel. The results of the experiment confirm that the bitstreams generated by the XSR circuit exhibit no autocorrelation and that there is no correlation between the bitstreams.

Transmission Line Effects of Long Gate-to-Gate Interconnections in Adiabatic Quantum-Flux-Parametron Logic Circuits

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family that utilizes adiabatic switching of logic gates. At present, a pure inductance is used to model a gate-to-gate interconnection in AQFP logic circuits. However, it is necessary to consider the transmission line effects when the interconnection length becomes long to take into account the propagation delay. This study investigated the transmission line effects of a long gate-to-gate interconnection in AQFP logic circuits. We observed reflection effects in a long transmission line between AQFP gates. These effects induced errors when the interconnection length exceeded several hundred micrometers. We adopted a damping resistance to stabilize the reflection effect to realize an error-free long gate-to-gate interconnection. The circuit simulations confirmed that a damping resistance connected in parallel to the transmission line effectively stabilizes the reflection effect, enabling an interconnection length that is longer than 1 mm. We fabricated AQFP buffer chains that included a long transmission line with and without a parallel damping resistance, and measured their bit error rates. The results showed that the parallel damping resistance effectively improves the bit error rate at high frequencies.

Design and Demonstration of a Superconducting Field-Programmable Gate Array Using Adiabatic Quantum-Flux-Parametron Logic and Memory

Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient, high- performance information processing systems because it has significantly low power consumption due to the adiabatic switching of Josephson junctions. We are developing a high-performance field-programmable gate array (FPGA) using superconducting AQFP circuits to reduce its energy consumption. The all-AQFP FPGA consists of logic blocks, switch blocks, connection blocks, and memory using AQFP circuits. In particular, the memory is composed of AQFP buffer chains, enabling high-density and low-power memory. The switch blocks can perform data routing as well as several logic functions, including majority, <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">and</small> , and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">or</small> functions, which increases the design flexibility of the all-AQFP FPGA. We fabricated a one-unit all-AQFP FPGA and demonstrated its reconfigurable operation at low speed. It was found that much lower power consumption can be achieved in the new FPGA than in the other superconducting FPGAs.

High-fidelity circuit simulation of AQFP circuits through compact models extracted from layout

Adiabatic Quantum Flux Parametron (AQFP) superconductor logic circuits rely on magnetic coupling between the gate and clock and control lines to function. Circuit designers start by designing a circuit netlist, selecting parameters to fit design objectives, optimizing the netlist in simulation and then progressing to integrated circuit layout. Hand-designed netlists mostly do not contain all the mutual inductances between inductors. The lack of a complete set of mutual inductances can limit the accuracy of the designed netlist. For a circuit netlist to be an exact representation of the layout, the number of inductors should be equal to the number of fundamental cycles in the netlist graph and all inductors should be coupled. In this paper, we show that full-circuit inductance extraction of AQFP layout where self and mutual inductances are specified by the designer produces small but possibly significant errors due to mismatch between the design schematic and the layout. With compact simulation model extraction, which we added to the InductEx tool chain, a much more accurate simulation model that includes all mutual inductances can be obtained to verify circuit performance after layout. We propose compact model extraction as the final step in cell library characterisation.

A High-Speed Interface Based on a Josephson Latching Driver for Adiabatic Quantum-Flux-Parametron Logic

The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1 GHz and 4 GHz, respectively.

Adiabatic Quantum-Flux-Parametron: A Tutorial Review

The adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic element based on the quantum flux parametron. AQFP circuits can operate with energy dissipation near the thermodynamic and quantum limits by maximizing the energy efficiency of adiabatic switching. We have established the design methodology for AQFP logic and developed various energy-efficient systems using AQFP logic, such as a low-power microprocessor, reversible computer, single-photon image sensor, and stochastic electronics. We have thus demonstrated the feasibility of the wide application of AQFP logic in future information and communications technology. In this paper, we present a tutorial review on AQFP logic to provide insights into AQFP circuit technology as an introduction to this research field. We describe the historical background, operating principle, design methodology, and recent progress of AQFP logic.

A 16-Bit Parallel Prefix Carry Look-Ahead Kogge-Stone Adder Implemented in Adiabatic Quantum-Flux-Parametron Logic

Extremely energy-efficient logic devices are required for future low-power high-performance computing systems. Superconductor electronic technology has a number of energy-efficient logic families. Among them is the adiabatic quantum-flux-parametron (AQFP) logic family, which adiabatically switches the quantum-flux-parametron (QFP) circuit when it is excited by an AC power-clock. When compared to state-of-the-art CMOS technology, AQFP logic circuits have the advantage of relatively fast clock rates (5 GHz to 10 GHz) and 5 - 6 orders of magnitude reduction in energy before cooling overhead. We have been developing extremely energy-efficient computing processor components using the AQFP. The adder is the most basic computational unit and is important in the development of a processor. In this work, we designed and measured a 16-bit parallel prefix carry look-ahead Kogge-Stone adder (KSA). We fabricated the circuit using the AIST 10 kA/cm2 High-speed STandard Process (HSTP). Due to a malfunction in the measurement system, we were not able to confirm the complete operation of the circuit at the low frequency of 100 kHz in liquid He, but we confirmed that the outputs that we did observe are correct for two types of tests: (1) critical tests and (2) 110 random input tests in total. The operation margin of the circuit is wide, and we did not observe any calculation errors during measurement.

Design of Hybrid Counter using Adiabatic Quantum Flux Parametron

Power consumption is one of the most considered factors while designing any electronics digital circuit. In which, the Adiabatic Quantum Flux parametron (AQFP) is one of the best superconducting technology for reduced power factor. Adiabatic Quantum Flux Parametron (AQFP) will be powered by the use of AC (Alternating Current) in place of DC power supply. In this research article, a hybrid counter is designed based on Adiabatic Quantum Flux Parametron (AQFP). The hybrid counter is modelled using parallel counter circuits. This counter is designed based on different stages of manipulation. The different stages are based on the number of bits used in the design. Here the design is made up of 4 - bit hybrid counter with four stages of computation and due to these stages of computation, the computation cost is reduced up to 28% compared to existing semiconductor counter electronics circuits. Since the computation cost is reduced, which directly implies that the speed of design is high speed and power is also reduced in huge factors in range of nanowatts.

Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor logic family. AQFP logic gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement an energy-efficient switching process, adiabatic switching. We have proposed a low-latency clocking scheme, delay-line clocking, and demonstrated basic AQFP logic gates. In order to test more complex circuits, a serializer/deserializer (SerDes) should be incorporated into the AQFP circuit under test, since the number of input/output (I/O) cables is limited by equipment. Therefore, in the present study we propose and develop a novel SerDes for testing delay-line-clocked AQFP circuits by combining AQFP and rapid single-flux-quantum (RSFQ) logic families, which we refer to as the AQFP/RSFQ hybrid SerDes. The hybrid SerDes comprises RSFQ shift registers to facilitate the data storage during serial-to-parallel and parallel-to-serial conversion. Furthermore, all the component circuits in the hybrid SerDes are clocked by the identical excitation current to synchronize the AQFP and RSFQ parts. We fabricate and demonstrate a delay-line-clocked AQFP circuit (8-to-3 encoder, which is the largest delay-line-clocked circuit ever designed) integrated with the hybrid SerDes at 4.2 K up to 4.5 GHz. Our measurement results indicate that the hybrid SerDes enables the testing of delay-line-clocked AQFP circuits with only a few I/O cables and is thus a powerful tool for the development of very large-scale integration AQFP circuits.