Addressable Test Structure Research Articles

A VDD Correction Method for Static Stability Test of SRAM Bit Cell

SRAM stability is a major concern in nanometer CMOS technologies. As the most important metrics of SRAM static stability, the static characteristics of SRAM are derived by static characteristic curves (read butterfly curve, standby butterfly curve, read N curve, write N curve and WNM curve). This paper deduces the read butterfly curve transfer function as an example to show the effect of supply voltage deviation. In order to increase the quantity of SRAM DUTs (Device under Tests) and test accuracy, we propose a test method with VDD correction which eliminates the effect of supply voltage deviation. First, an addressable test structure is applied, where the transmission gates are used to force and sense the node voltages, and then correct the voltages. Second, a test algorithm with fast convergence combining the bisection method and PID (Proportion Integral Differential) algorithm is proposed to correct the voltages. SPICE simulations show that the proposed method reduces the error from approximately 10% (commonly used methods) to less than 2%. It is further implemented in a standard 55nm CMOS process, and the static characteristic curves of 1k-bits SRAM DUTs are measured within the accuracy range of 1 mV, which fit well with the simulation results, indicating the method can accurately measure 1k-bits DUTs.

Novel Addressable Test Structure for Detecting Soft Failure of Resistive Elements When Developing Manufacturing Procedures

A novel addressable test structure for detecting soft failures of resistive elements is proposed. Its architecture is much simpler than that of previous works, but all functions needed to analyze the electrical properties of detected failures, for example, the aging test with overcurrent, can be realized within the architecture. This makes it more powerful than previous designs. Since the addressable test structure proposed here also has a smaller footprint, it can realize cost effective evaluations.

Design of the Addressable Test Structure for ${S}$ -Parameter-Based RF Device Characterization

This paper presents an addressable measurement method for ${S}$ -parameters characterization. To achieve this concept, compact transmit/receive (T/R) switches with radio frequency (RF)-oriented layout pattern are implemented to construct addressable signal paths. A customized deembedding method is performed to extract ${S}$ -parameters with acceptable accuracy. Thanks to the addressable structure which significantly eliminates unnecessary contact pads in RF device characterization, much less silicon area is required. Several prototypes, including nonaddressable and addressable test structures with different devices-under-test, have been fabricated using a commercial 0.13- $\mu \text{m}$ CMOS technology. Measurement results suggest that the proposed addressable test structure is able to provide accurate ${S}$ -parameters measurements at gigahertz range consuming about 50% less silicon area.

Analysis of Soft Failures in Low-Resistance Interconnect Vias Using Doubly Nesting Arrays

An addressable test structure array for detecting soft failures in interconnect vias was developed. Resistive elements exhibiting abnormally high resistance are detected, while suppressing the measurement time, using a doubly nesting array structure. Applying this technique to the development of a 40-nm CMOS technology, a soft failure with about ten times larger than normal via resistance could be efficiently detected and located.

4719411 Addressable test matrix for measuring analog transfer characteristics of test elements used for integrated process control and device evaluation

A set of addressable test structures, each of which uses addressing schemes to access individual elements of the structure in a matrix, is used to test the quality of a wafer before integrated circuits produced thereon are diced, packaged and subjected to final testing. The electrical characteristic of each element is checked and compared to the electrical characteristic of all other like elements in the matrix. The effectiveness of the addressable test matrix is in readily analyzing the electrical characteristics of the test elements and in providing diagnostic information.