Address Mapping Scheme Research Articles

Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping

The DRAM performance has become a critical bottleneck of modern computing systems. Prior studies have proposed various optimization techniques on address mapping to bridge the gap between real performance and the peak performance. Nevertheless, these techniques have some common limitations. First, most of them focus on an indirect metric (e.g., bitwise flip ratio) and fail to address the effects of complicated organization hierarchy and timing constraints of DRAM. Second, these approaches do not leverage application-specific information and may not generate the proper address mapping schemes for modern applications. In this article, we propose Flatfish as a comprehensive solution to address these challenges. Flatfish is a self-adaptive memory controller that is able to generate address mapping schemes according to the memory access pattern. Different from prior approaches, Flatfish considers complicated memory hierarchy, including channel, rank, and bank group and addressed critical timing constraints. By mining the characteristics from the memory access traces, Flatfish integrates a reinforcement learning model to generate a binary invertible matrix (BIM) as the address mapping scheme. Flatfish can work in either offline mode or online mode to meet various requirements in different scenarios. The experimental results show that Flatfish can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.91\times $ </tex-math></inline-formula> speedup in the offline mode on GPU, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.63\times $ </tex-math></inline-formula> speedup in the online mode on CPU, over the commonly used Hynix address mapping scheme.

IBU: An In-Block Update Address Mapping Scheme for Solid-State Drives

IBU: An In-Block Update Address Mapping Scheme for Solid-State Drives

Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller

Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.

MEG

Emerging three-dimensional (3D) memory technologies, such as the Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM), provide high-bandwidth and massive memory-level parallelism. With the growing heterogeneity and complexity of computer systems (CPU cores and accelerators, etc.), efficiently integrating emerging memories into existing systems poses new challenges and requires detailed evaluation in a realistic computing environment. In this article, we propose MEG, an open source, configurable, cycle-exact, and RISC-V-based full-system emulation infrastructure using FPGA and HBM. MEG provides a highly modular hardware design and includes a bootable Linux image for a realistic software flow, so that users can perform cross-layer software-hardware co-optimization in a full-system environment. To improve the observability and debuggability of the system, MEG also provides a flexible performance monitoring scheme to guide the performance optimization. The proposed MEG infrastructure can potentially benefit broad communities across computer architecture, system software, and application software. Leveraging MEG, we present two cross-layer system optimizations as illustrative cases to demonstrate the usability of MEG. In the first case study, we present a reconfigurable memory controller to improve the address mapping of standard memory controller. This reconfigurable memory controller along with its OS support allows us to optimize the address mapping scheme to fully exploit the massive parallelism provided by the emerging three-dimensional (3D) memories. In the second case study, we present a lightweight IOMMU design to tackle the unique challenges brought by 3D memory in providing virtual memory support for near-memory accelerators. We provide a prototype implementation of MEG on a Xilinx VU37P FPGA and demonstrate its capability, fidelity, and flexibility on real-world benchmark applications. We hope MEG fills a gap in the space of publicly available FPGA-based full-system emulation infrastructures, specifically targeting memory systems, and inspires further collaborative software/hardware innovations.

An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems

A modern memory system is equipped with many memory channels to obtain a high memory bandwidth. To take the advantage of this organization, applications’ data are distributed among the channels and transferred in an interleaved fashion. Although memory-intensive applications benefit from a high bandwidth by many memory channels, applications such as compute-intensive ones do not need the high bandwidth. To reduce the energy consumption for such applications, the memory system has low-power modes. During no memory request, the main memory can enter these modes and reduce energy consumption. However, these applications often cause intermittent memory requests to the channels that handle their data, resulting in not entering the low-power modes. Hence, the memory system cannot enter the low-power modes even though the applications do not need the high bandwidth. To solve this problem, this paper proposes a dynamic data allocation mechanism for many-channel memory systems. This mechanism forces data of such applications to use the specified channels by dynamically changing the address-mapping schemes and migrating the data. As a result, the other channels to which the data are not allocated can have a chance to enter the low-power modes for a long time. Therefore, the proposed mechanism has the potential to reduce the energy consumption of many-channel memory systems. The evaluation results show that this mechanism can reduce the energy consumption by up to 11.8% and 1.7% on average.

DPAM: A Demand-Based Page-Level Address Mappings Algorithm in Flash Memory for Smart Industrial Edge Devices

Edge computing brings data storage closer to the location where it is needed. Therefore, the edge devices, especially smart industrial edge devices, require higher storage systems. NAND flash memory has the advantages of small size, high speed, and strong shock resistance, which is widely used in various storage systems, providing a good choice for edge devices. NAND flash has unique physical characteristics, such as “out-of-place updates” and “prewrite erasure,” therefore, the traditional address mapping methods require improvement. This article presents a novel demand-based page-level address mapping algorithm called DPAM. The goal of DPAM is to provide efficient address translation by using a smaller address mapping table. Due to the high service cost of block-level address mapping and hybrid address mapping, a page-level address mapping scheme is proposed. The algorithm is implemented and tested on the flash simulation platform FlashSim. The results indicate that our algorithm provides improvements of 7.11% for the hit ratio and 7% for the number of block erasures compared with other approaches.

An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache

NAND flash memory has been the default storage component in embedded systems. One of the key technologies for flash management is the address mapping scheme between logical addresses and physical addresses, which deals with the inability of in-place-updating in flash memory. Demand-based page-level mapping cache is often applied to match the cache size constraint and performance requirement of embedded storage systems. However, recent studies showed that the management overhead of mapping cache schemes is sensitive to the host I/O patterns, especially when the mapping cache is small. This paper presents a novel I/O scheduling scheme, called MAP+, to alleviate this problem. The proposed scheduling approach reorders I/O requests for performance improvement from two angles. Prioritizing the requests that will hit in the mapping cache, and grouping requests with related logical addresses into large batches. Batches of requests are reordered to further optimize request waiting time. Experimental results show that MAP+ improved upon traditional I/O schedulers by 48% and 18% in terms of read and write latencies, respectively.

Impacts of Memory Address Mapping Scheme on Reducing DRAM Self-Refresh Power for Mobile Computing Devices

With the growth of the Internet of Things (IoT), increasingly, more computing tasks are implemented on power-sensitive mobile devices, causing a bottleneck on energy consumption. Most mobile devices consume considerable power in the standby mode, during which the capacitive DRAM cells’ self-refresh power, which is used to preserve data integrity, accounts for a large part. To address this issue, strategies from both hardware and software perspectives have been proposed, and yet, the existing hardware methods usually have a high cost. Software strategies mainly focus on the operating system page allocation strategy to maximize resource idleness. The partial array self-refresh technique has been proposed to allow for some of the DRAM cells to retain the self-refresh state while shutting down the others. Using this technique, numerous studies extend the unused DRAM idle time by clustering the applications’ data but do not discuss the impact of the address mapping mechanism on power consumption. However, this impact was proven to be essential in our previous study. In this paper, we attempt to investigate the impacts of different memory mapping schemes on different clustering strategies using a hierarchy-based memory management system (HBMM) and provide insights for selecting the optimal schemes. The experimental results on the Android platform demonstrate that the schemes and strategies are closely correlated, and memory idle time can be prolonged 125 times with their suitable combination. Conversely, the worst scheme may decrease memory idleness by 12% compared with the original system. Furthermore, our studies on a physical platform show that standby power consumption can be saved by 23% when using HBMM combined with the best clustering strategy.

A Continuous-Flow Memory-Based Architecture for Real-Valued FFT

This brief proposes a continuous-flow memory-based architecture for fast Fourier transform (FFT) computation for real-valued signals. The proposed architecture is based on a modified radix-2 algorithm, which removes redundant operations to reduce resource usage. A new data-flow graph and address mapping scheme are proposed that satisfy the requirement of continuous-flow operation and minimize the memory usage. The proposed processing element takes advantage of pipelined FFT architectures to avoid bank conflicts in each stage. Compared with prior works, the proposed design has the advantage of supporting continuous-flow operation and normal-order output while minimizing the resource usage.

Design Tradeoffs of SSDs

In this work, we studied the energy consumption characteristics of various SSD design parameters. We developed an accurate energy consumption model for SSDs that computes aggregate, as well as component-specific, energy consumption of SSDs in sub-msec time scale. In our study, we used five different FTLs (page mapping, DFTL, block mapping, and two different hybrid mappings) and four different channel configurations (two, four, eight, and 16 channels) under seven different workloads (from large-scale enterprise systems to small-scale desktop applications) in a combinatorial manner. For each combination of the aforementioned parameters, we examined the energy consumption for individual hardware components of an SSD (microcontroller, DRAM, NAND flash, and host interface). The following are some of our findings. First, DFTL is the most energy-efficient address-mapping scheme among the five FTLs we tested due to its good write amplification and small DRAM footprint. Second, a significant fraction of energy is being consumed by idle flash chips waiting for the completion of NAND operations in the other channels. FTL should be designed to fully exploit the internal parallelism so that energy consumption by idle chips is minimized. Third, as a means to increase the internal parallelism, increasing way parallelism (the number of flash chips in a channel) is more effective than increasing channel parallelism in terms of peak energy consumption, performance, and hardware complexity. Fourth, in designing high-performance and energy-efficient SSDs, channel switching delay, way switching delay, and page write latency need to be incorporated in an integrated manner to determine the optimal configuration of internal parallelism.

Z-MAP

Existing space management and address mapping schemes for flash-based Solid-State-Drive (SSD) operate either at page or block granularity, with inevitable limitations in terms of memory requirement, performance, garbage collection, and scalability. To overcome these limitations, we proposed a novel space management and address mapping scheme for flash referred to as Z-MAP, which manages flash space at granularity of Zone. Each Zone consists of multiple numbers of flash blocks. Leveraging workload classification, Z-MAP explores Page-mapping Zone (Page Zone) to store random data and handle a large number of partial updates, and Block-mapping Zone (Block Zone) to store sequential data and lower the overall mapping table. Zones are dynamically allocated and a mapping scheme for a Zone is determined only when it is allocated. Z-MAP uses a small part of Flash memory or phase change memory as a streaming Buffer Zone to log data sequentially and migrate data into Page Zone or Block Zone based on workload classification. A two-level address mapping is designed to reduce the overall mapping table and address translation latency. Z-MAP classifies data before it is permanently stored into Flash memory so that different workloads can be isolated and garbage collection overhead can be minimized. Z-MAP has been extensively evaluated by trace-driven simulation and a prototype implementation on OpenSSD. Our benchmark results conclusively demonstrate that Z-MAP can achieve up to 76% performance improvement, 81% mapping table reduction, and 88% garbage collection overhead reduction compared to existing Flash Translation Layer (FTL) schemes.

Memory efficient and scalable address mapping for flash storage devices

Flash memory devices commonly rely upon traditional address mapping schemes such as page mapping, block mapping or a hybrid of the two. Page mapping is more flexible than block or hybrid mapping without being restricted by block boundaries. However, its mapping table tends to grow large quickly as the capacity of flash memory devices does. To overcome this limitation, we propose novel mapping schemes that are fundamentally different from the existing mapping strategies. We call these new schemes Virtual Extent Trie (VET) and Extent Mapping Tree (EMT), as they manage mapping information by treating each I/O request as an extent and by using extents as basic mapping units rather than pages or blocks. By storing extents instead of individual addresses, our extent mapping schemes consume much less memory to store mapping information and still remain as flexible as page mapping. We observed in our experiments that our schemes reduced memory consumption by up to an order of magnitude in com- parison with the traditional mapping schemes for several real world workloads. Our extent mapping schemes also scaled well with increasing address spaces by synthetic workloads. Even though the asymp- totic mapping cost of VET and EMT is higher than the O(1) time of a page mapping scheme, the amount of increased overhead was almost negligible or low enough to be hidden by an accompanying I/O operation.

On-Demand Block-Level Address Mapping in Large-Scale NAND Flash Storage Systems

The density of flash memory chips has doubled every two years in the past decade and the trend is expected to continue. The increasing capacity of NAND flash memory leads to large RAM footprint on address mapping management. This paper proposes a novel Demand-based block-level Address mapping scheme with a two-level Caching mechanism (DAC) for large-scale NAND flash storage systems. The objective is to reduce RAM footprint without excessively compromising system response time. In our technique, the block-level address mapping table is stored in fixed pages (called the translation pages) in the flash memory. Considering temporal locality that workloads exhibit, we maintain one cache in RAM to store the on-demand address mapping entries. Meanwhile, by exploring both spatial locality and access frequency of workloads with another two caches, the second-level cache is designed to cache selected translation pages. In such a way, both the most-frequently-accessed and sequentially accessed address mapping entries can be stored in the cache so the cache hit ratio can be increased and the system response time can be improved. To the best of our knowledge, this is the first work to reduce the RAM cost by employing the demand-based approach on block-level address mapping schemes. The experiments have been conducted on a real embedded platform. The experimental results show that our technique can effectively reduce the RAM footprint while maintaining similar average system response time compared with previous work.

Design and Simulation of FFT Processor Using Radix-4 Algorithm Using FPGA

A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM) and WLAN, unlike being stored in the traditional ROM. The twiddle factors in our pipelined FFT processor can be accessed directly. A novel simple address mapping scheme and the modified radix 4 FFT also proposed. FPGA was majorly used to develop the ASIC IC’s to which was implemented. Here we simulated and synthesized the 256- point FFT with radix-4 using VHDL coding and 64 point FFT Hardware implementation we designed code using System C. Finally, the pipelined 256-point FFT processor can be completely implemented within 19.103ns.

E 3 CC: A memory error protection scheme with novel address mapping for subranked and low-power memories

This study presents and evaluates E 3 CC (Enhanced Embedded ECC), a full design and implementation of a generic embedded ECC scheme that enables power-efficient error protection for subranked memory systems. It incorporates a novel address mapping scheme called Biased Chinese Remainder Mapping (BCRM) to resolve the address mapping issue for memories of page interleaving, plus a simple and effective cache design to reduce extra ECC traffic. Our evaluation using SPEC CPU2006 benchmarks confirms the performance and power efficiency of the E 3 CC scheme for subranked memories as well as conventional memories.

Using SDRAM Memories for High-Performance Accesses to Two-Dimensional Matrices Without Transpose

The data throughput of SDRAMs is significantly reduced by the control overhead required for access or transposition of large two-dimensional data matrices stored in SDRAM memories. In this paper, a new address mapping scheme is introduced, taking advantage of multiple banks and burst capabilities of modern SDRAMs. In this way, the data throughput is maximized when reading or writing rows or columns of a two-dimensional data matrix. Other address mapping strategies minimize the total number of SDRAM page-opens while traversing the two-dimensional index-space in row or column direction. In order to achieve a higher data throughput, the new approach uses an alternative bank interleaving method to hide additional wait cycles. In this way, the number of data bus wait cycles do not depend on the overall number of page-opens directly any more. It is shown, that the data bus utilization can be increased significantly. In particular, the new mapping strategy is optimized for access of parallel samples, distributed among a number of SDRAM chips. Therefore, double buffering can be omitted. As a special operation, 2D-FFT processing for radar applications is considered. Depending on SDRAM parameters and dimensions, a continuous bandwidth utilization of 96–98 % is achieved for accesses in both matrix dimensions, including all page-opens and refresh operations.

Performance Analysis of FTL Schemes

Today Nand Flash memory is not only used in hand hold electronic devices but also as secondary storage medium. It serves as an alternative to Hard Disk Drives (HDDs) in the form of Solid State Dives (SDDs). However, unlike HDD flash memory does not support in place update, i.e. for updating data, old data can not be replaced by new data. Data can be written only at clean i.e. already erased place. This is called as erase before update. This erase before update nature of Nand Flash memory is kept hidden with the help of a functionality called as address mapping or address translation. Many efforts for optimizing the working of address mapping schemes have been done by different research workers. Though various schemes are designed and proposed but there is no literature available providing mathematical computations comparing the performance of the various mapping schemes in the form of time complexity. In this paper we have tried to find out the comparative cost of block merge operation required during garbage collection for some representative mapping schemes like BAST [9] and FAST [7]. This paper also presents a review of all these schemes and presents a comparative trade offs among all these major schemes. The paper is divided into five sections: section 1 is introduction of Flash memory, section 2 describes various mapping schemes and presents their comparative performance, Section 3 does the conclusion. Section 4 is acknowledgement and section 5 describes the future scope.

동적 사상 테이블 기반의 버퍼구조를 통한 Solid State Disk의 쓰기 성능 향상

본 연구는 플래시 메모리 기반의 고성능 SSD (Solid State Disk) 구조를 위하여 디스크 참조 특성에 적응적으로 구동하는 효율적인 버퍼 구조와 구동 기법을 설계한다. 기존 SSD는 삭제동작 횟수의 제약은 물론 읽기와 쓰기 동작에 대하여 비대칭적인 성능을 보이는 특징을 갖고 있다. 이러한 삭제동작 횟수와 쓰기 동작의 지연시간을 최소화 하기 위해서는 다중 플래시 메모리 칩들에 대해 쓰기 동작은 병렬적으로 수행하는 정도를 최대화하여 운영하여야 한다. 따라서 플래시 메모리 칩들에 대한 인터리빙 레벨 (interleaving level)을 최대화 하기 위하여, 본 논문에서는 혼합 위치 사상 기법 (hybrid address mapping)과 슈퍼 블록 (super-block) 기반의 SSD 구조에 대하여 성능 증대와 증가된 장치 수명을 제공하기 위한 효율적 버퍼 구조를 제안한다. 제안한 버퍼구조는 응용 수행특성을 기반으로 최적의 임의/순차쓰기를 구분하며, 수행 성능에 중요한 순차쓰기 정도의 크기를 증대시키는 동적 융합 방법, 구동되는 버퍼구조와 사상 테이블의 효율적인 관리 구조를 설계하였으며, 이를 통해 기존의 단순한 버퍼 운영기법에 비하여 35%의 성능향상을 제공한다. This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.

Security refresh

Phase change memory (PCM) is an emerging memory technology for future computing systems. Compared to other non-volatile memory alternatives, PCM is more matured to production, and has a faster read latency and potentially higher storage density. The main roadblock precluding PCM from being used, in particular, in the main memory hierarchy, is its limited write endurance. To address this issue, recent studies proposed to either reduce PCM's write frequency or use wear-leveling to evenly distribute writes. Although these techniques can extend the lifetime of PCM, most of them will not prevent deliberately designed malicious codes from wearing it out quickly. Furthermore, all the prior techniques did not consider the circumstances of a compromised OS and its security implication to the overall PCM design. A compromised OS will allow adversaries to manipulate processes and exploit side channels to accelerate wear-out. In this paper, we argue that a PCM design not only has to consider normal wear-out under normal application behavior, most importantly, it must take the worst-case scenario into account with the presence of malicious exploits and a compromised OS to address the durability and security issues simultaneously. In this paper, we propose a novel, low-cost hardware mechanism called Security Refresh to avoid information leak by constantly migrating their physical locations inside the PCM, obfuscating the actual data placement from users and system software. It uses a dynamic randomized address mapping scheme that swaps data using random keys upon each refresh due. The hardware overhead is tiny without using any table. The best lifetime we can achieve under the worst-case malicious attack is more than six years. Also, our scheme incurs around 1% performance degradation for normal program operations.

CFTL

The flash translation layer (FTL) is a software/hardware in terface inside NAND flash memory. Since FTL has a critical impact on the performance of NAND flash-based devices, a variety of FTL schemes have been proposed to improve their performance. In this paper, we propose a novel hybrid FTL scheme named Convertible Flash Translation Layer (CFTL). Unlike other existing FTLs using static address mapping schemes, CFTL is adaptive to data access patterns so that it can dynamically switch its mapping scheme to either a read-optimized or a write-optimized mapping scheme. In addition to this convertible scheme, we propose an efficient caching strategy to further improve the CFTL performance with only a simple hint. Consequently, both the convertible feature and the caching strategy empower CFTL to achieve good read performance as well as good write performance.