A Continuous-Flow Memory-Based Architecture for Real-Valued FFT

Abstract

This brief proposes a continuous-flow memory-based architecture for fast Fourier transform (FFT) computation for real-valued signals. The proposed architecture is based on a modified radix-2 algorithm, which removes redundant operations to reduce resource usage. A new data-flow graph and address mapping scheme are proposed that satisfy the requirement of continuous-flow operation and minimize the memory usage. The proposed processing element takes advantage of pipelined FFT architectures to avoid bank conflicts in each stage. Compared with prior works, the proposed design has the advantage of supporting continuous-flow operation and normal-order output while minimizing the resource usage.