Address Discharge Time Lag Research Articles

Effect of the Driving Waveform With Negative-Going Ramp on the Address Discharge Characteristics of Plasma Display Panel With High-Gamma Cathode Material

The address discharge characteristics of the plasma display with a MgO single cathode layer and the one with a MgO-SrO double cathode layer were investigated. In particular, the conventional waveform with a positive-going ramp and the proposed waveform with a negative-going ramp were applied in order to demonstrate that the polarity of the scan electrode during the reset period affects the dynamic voltage margin and the address discharge time lag. It was confirmed that the total address discharge time lag of the plasma display with the MgO-SrO double cathode layer decreased by about 550 ns by applying the proposed waveform with the negative-going ramp.

7.2: Fast‐Addressing Waveform with Negative‐Going Ramp for High‐Xe PDP with High‐Gamma Cathode Materials

AbstractIn this paper, the address discharge characteristics of high‐Xe PDPs with high‐gamma cathode materials were investigated. It will be shown that the address discharge characteristics such as the dynamic voltage margin and the address discharge time lag of high‐Xe PDP with MgO‐SrO double cathode layer and one with MgCaO single cathode layer can be improved by inducing stable, continuous weak discharges during the reset period with a newly designed waveform. The deposition of pure MgO powder on high gamma cathode material has also proved to be effective in reducing the address discharge time lag of high‐Xe PDP.

Study on Address Discharge Characteristics by Changing Ramp-Down Voltage in AC PDPs

The address discharge characteristics formed when an address pulse is applied in AC plasma display panels are investigated by changing the ramp-down voltage during the reset period. The address discharge time lag can be reduced when the difference between the ramp-down voltage and the scan-low voltage is set at a high value during the ramp-down period because the loss of the wall charges accumulated between the scan (Y) and address (A) electrodes during the reset period is minimized. In addition, the voltage applied to the X electrode during the ramp-down period can prevent the voltage margin from reduction even though applying high voltage difference on the Y electrodes.

Influence of Gold Nanoparticles on the Characteristics of Plasma Display Panels

This paper proposes a modified alternating current plasma display panel (PDP) in which gold nanoparticles are incorporated into a bare MgO layer to enhance the performance of the protective layer. The proposed structure's ion-induced secondary electron yield, which is expressed in a gamma value ( value) is greater than that of a bare MgO layer; as a result, the operating voltage decreases by 10 V to 20 V. The integration of emitted infrared (IR) light and the power density consumed by the discharge current are both increased, but the ratio of increment is greater for the case of the IR light. Consequently, IR efficacy is increased. The IR response time of the sustain discharge and the address discharge time lag are reduced by the enhanced wall charge accumulation characteristic and the exoelectron emission property. The results of ultraviolet photoelectron spectroscopy show that a MgO layer with Au nanoparticles has a lower work function than a conventional bare MgO layer. Furthermore, the structure that is not flattened by nanoparticles seems to enhance the secondary electron emission property of the MgO protective layer. Consequently, the value is enhanced by the two reasons previously mentioned.

Fe가 첨가된 MgO 보호막의 표면특성 개선에 관한 연구

플라즈마 디스플레이 패널(Plasma Display Panel : PDP)이 다른 평판 디스플레이 분야(Liquid Crystal Displays(LCDs) and organic light emitting diodes(OLEDs) 등)와 경쟁에서 이기기 위해서는 제품의 고화질화, 저소비전력와 고속구동 등의 성능향상이 필요하다. 본 논문에서는 PDP의 성능향상을 위하여 유전체 보호층으로 쓰이는 MgO 박막에 Fe를 미량 첨가한 박막을 증착하고, 그 특성에 대하여 연구하였다. e-beam 증착법으로 증착된 Fe 도핑 된 MgO 박막의 표면특성과 전기광학적 특성을 4인치 테스트 패널을 제작하여 연구하였다. Fe가 도핑된 MgO 박막을 가지는 PDP는 Fe가 도핑되지 않은 PDP에 비해 낮은 방전전압 특성을 나타내었으며, 이는 박막에서 측정된 2차전자방출계수의 실험결과와 잘 일치되었다. 증착된 박막의 결정성과 표면 거칠기는 XRD 와 AFM 측정방법을 통하여 결정되었다. 또한, Fe가 도핑된 PDP는 고속구동을 위한 향상된 어드레스 방전 늦음의 특성을 나타내었다.

Improved discharge time lag of address pulse in an ACPDP with auxiliary electrodes

Abstract— New driving waveforms are proposed for an ACPDP with an auxiliary electrode. Auxiliary pulses and a stepped scan pulse during the address period distinguish the proposed waveforms from conventional waveforms. The address discharge time lag in an ACPDP with auxiliary electrodes was improved by application of auxiliary pulses and a stepped scan pulse during the address period. The interaction between the auxiliary pulse and the stepped scan pulse generates priming particles directly prior to the address discharge, and these priming particles influence the address discharge. As a result, the firing voltage of the address pulse is lowered, and the minimum address voltage is lower than that of conventional driving waveforms. Experimental results confirm that the address discharge time lag of the proposed waveforms is 32% lower than that of conventional driving waveforms.

Driving Characteristics of a High-Efficacy AC PDP With an Auxiliary Electrode

A new driving waveform was proposed in order to stabilize the driving characteristics of a high-efficacy AC plasma-display panel (PDP) with a coplanar gap of 200 mum and an auxiliary electrode. To stabilize the reset and address discharge, an erase pulse was applied to the auxiliary electrode instead of the sustain electrode after the sustain period. The write pulse was applied to the scan electrode, and a reset discharge was induced between the scan and auxiliary electrodes. As a result, the minimum address voltage could be reduced to a level similar to that achieved with a conventional ac PDP with a coplanar gap of 80 mum. Furthermore, the address-discharge time lag of the ac PDP with a coplanar gap of 200 mum was improved to a level that is comparable with that of the ac PDP with a coplanar gap of 80 mum.

P‐138: Driving Waveforms for Reducing Address Discharge Time Lag in an AC PDP with Auxiliary Electrodes

AbstractThe address discharge time lag in an AC PDP with auxiliary electrodes was improved by applying auxiliary pulses and a stepped scan pulse during the address period. Interaction between the auxiliary pulse and the stepped scan pulse generated priming particles during the address period, influencing the address discharge positively. As a result, the minimum address voltage was reduced, and was lower than that of conventional driving waveforms. Furthermore, when the proposed waveforms were applied, the address discharge time lag was improved by 32% compared to that of the conventional driving waveforms with the same address voltage.

The Operation Characteristics of an Alternating Current Plasma Display Panel With Si-Doped MgO Protecting Layer

In this paper, the operation characteristics of an ac plasma display panel (PDP) with Si-doped MgO protecting layer are investigated. The test panels are fabricated with the protecting layers of conventional MgO and Si-doped MgO, and the operation voltage margin, luminous efficacy, and address discharge time lag are observed. Even though the test panel with Si-doped MgO protecting layer showed lower operation voltages, higher luminous efficacy, and shorter statistical discharge time lag, its addressing discharge characteristics become deteriorated as the scanning time is increased from the end time of the reset period. The photon-induced surface conductivity increased by Si doping into MgO, and surface charges on the Si-doped MgO protecting layer showed faster decay characteristics compared to those on the conventional one. It is believed that the impurity doping into the protecting layer can improve the short-period characteristics of an ac PDP, but the long-term stability of surface charge retention is deteriorated.

High‐speed driving waveform based on reset and address discharge analysis using a Vt closed curve in ACPDPs

Abstract— Driving waveforms having both high‐speed address and low background were developed using Vt closed curve analysis. To prevent a misfired discharge during a sustain period, the voltage difference at the end of the ramp setup between the X‐Y electrodes remains constant. Because background luminance becomes higher (although the address discharge time lag becomes shorter) as the voltage difference between the A‐Y electrodes becomes larger, a low reset voltage and an address bias voltage were adopted during the ramp‐up period.

55.3: Study on Address Discharge Characteristics Using Vt Close‐Curve Analysis in ac PDPs

AbstractThe address discharge characteristics by the various scan‐low and common‐bias voltages are investigated based on measured address discharge time lags and Vt close‐curve analysis. The scan‐low voltages are changed with the same voltage difference between the X and Y electrodes during an address period, meaning that the voltage difference between the scan‐low voltage applied to the Y electrode and the common‐bias voltage applied to the X electrode remains constant even though each voltage level changes. As the voltage difference between the scan and address electrodes is increased during an address period, the address discharge time lag is shortened but a high background luminance is induced. It is found that the improved address discharge characteristics is caused by the effect of the higher external applied voltage during an address period than the accumulated wall charges during a reset period and the high background luminance can be prevented by applying an address‐bias voltage during a rising‐ramp period.

P‐204L: Late‐News Poster: Analysis of Statistical Time Lags Based on Wall Charges Prior to Address Discharge Using Vt Close‐Curve Method for Full‐HD AC‐PDP

AbstractThe high speed address is an important parameter to lower cost technology for the realization of full HD‐PDP. The wall charge supplied from the reset period is an important factor for affecting the fast and stable discharge characteristics during an address period. It is found that as the voltage level of the negative falling ramp in the reset waveform is lower, the accumulated wall charges during the ramp‐up period are more erased, thus reducing the amounts of wall charges prior to address discharge. The resultant changes in the address discharge characteristics were examined in the 42‐in. ac‐PDP with a high Xe (11 %) content. In particular, the measured Vt close‐curves and corresponding IR emission profiles show that less amounts of wall charges prior to an address discharge induce the decrease in the statistical time lag and total address discharge time lag in address period, thereby resulting in the stable and fast addressing. Therefore, it is advantageous to use the electric field from the applied voltage during an address discharge instead of utilizing the wall charges from the reset period for the stable and fast addressing.

Effects of Kr,$hboxN_2$, and Ar on Address Discharge Time Lag in AC Plasma-Display Panel With High Xenon Content

The additive gas effect on the discharge time lag of the address pulse was investigated in an ac plasma-display panel (PDP) with a Ne+13% Xe gas mixture. A small amount of Kr, N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and Ar gas, respectively, was added to a Ne+13% Xe gas mixture to improve the address discharge time lag of an ac PDP. It was found that the address discharge time lag was improved by adding a small amount of Kr gas (up to 2%) to the Ne+13% Xe gas mixture and thereafter worsened. In the case of the addition of Ar gas to Ne+13% Xe, the discharge time lag of the address pulse was not improved. The concentration of N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> in the Ne+13% Xe gas mixture was varied from 0.013% to 0.187%, and its effects on the address discharge time lag were investigated. The time lag for the address discharge with a Ne+13% Xe+0.013% N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gas mixture was improved

Characteristics of an address discharge time lag in terms of a wall voltage in an AC PDP

The characteristics of an address discharge have been investigated in terms of a wall voltage, which plays an important role in achieving a high-speed address discharge in an ac plasma display panel. The wall-voltage conditions generated in a reset period are a considerable factor to reduce the address-discharge time lag. Based on the experimental results, the reset driving scheme in which an address bias voltage is applied to the address electrode in a reset period is proposed to enhance the characteristics of an address-discharge time lag.

A new driving waveform for stable address discharge in an alternating current plasma display panels

Although the selective ramp reset waveform having one reset period during one television (TV)-field has a higher contrast ratio than the conventional ramp reset waveform with eight reset periods, the address discharge using the selective ramp reset waveform in a stripe barrier rib is severely influenced by the crosstalk. This problem of crosstalk among the cells constitutes the main obstacle to the development of high-resolution alternating current plasma display panels (AC-PDPs). In this paper, a new driving waveform is proposed, which renders the address discharge stable by decreasing the crosstalk, in addition to reducing the background luminance. In order to compare the address discharge stability of the proposed waveform with that of the conventional ramp reset waveform, we investigated the address discharge time lag through the photo-waveform measurement of address discharge for three waveforms and measured the dark room contrast ratio. As shown in the results, without decreasing the contrast ratio or the change of the panel structure, the address discharge time lag was considerably improved by the proposed waveform

P-111: New Driving Waveforms in AC PDP with Auxiliary Electrode

A new driving waveform was proposed to stabilize the reset and address discharges in the high efficacy AC PDP with coplanar-gap of 200 μm and auxiliary electrode. The erase pulse was applied to the auxiliary electrode after sustain period. The reset discharges were induced between scan and auxiliary electrode. During ramp-down period, a positive bias was applied to auxiliary and common electrode. The reset discharge of the coplanar-gap of 200 μm was stabilized. The address discharge time lag of the AC PDP with coplanar-gap of 200 μm was improved using the new driving waveforms. Also, it was found that the minimum address voltage could be reduced when the new driving waveforms were applied to the high efficacy PDP with auxiliary electrode.

A Driving Method for High-Speed Addressing in an AC PDP Using Priming Effect

A novel driving method is proposed to reduce the addressing time in an ac plasma display panel. In this method, priming discharges are used to achieve high-speed addressing without adding an auxiliary electrode. Some of the scan lines were used to provide the priming particles for the reduction of the address discharge time lag (t/sub d/) in the adjacent scan lines. The number of priming electrodes was optimized and two different types of priming discharge were tested in order to reduce the inherent light output caused by the priming discharges. In the panel experiment, the t/sub d/ was reduced to one half of that of the conventional method when the priming particles were provided and the background luminance was reduced from 4.97 to 2.94 cd/m/sup 2/ through the reduction of the number of priming electrodes, and further, by changing the type of the priming discharge while the peak luminance could be improved more than twice by allocating the saved-time-to-display period, which in turn, resulted in a higher contrast ratio.

Comparison of electric field and priming particle effects on address discharge time lag and addressing characteristics of high-xe content AC PDP

The alternating current plasma display panel (AC PDP) is generally driven by the subfield method to realize the gray scale, and each subfield is composed of reset, address and display period. Therefore, a significant time should be allocated to an address period in high-resolution PDP, which results in a short display period and a reduction of brightness, and so the dual scan method has been widely used to solve this problem. In this case, however, the address electrodes need to be physically divided into two parts and driven by different data drive integrated circuits (ICs), thereby causing a cost up due to doubling the number of data drive ICs. In this paper, we investigate the factors that could influence the address discharge time lag and, in particular, the electric field effects and priming particle effects are compared in order to achieve high speed addressing. In this regard, the address characteristics of high-Xe content panel are investigated from which it was found that the address discharge time lag was reduced to one half that of the conventional method when the priming particles are provided.

17.3: Improvement of the Speed of Address Discharges in Ne‐Xe‐He Discharge Gases for ACPDPs

AbstractThe time lag of address discharges is discussed in terms of its relation with discharge gas composition. We measured the discharge time lag in ACPDPs with Ne‐Xe‐He mixed gases. As the concentration of helium increases, the address discharge time lag becomes shortened because helium atoms reduce mostly the formative time lag of the discharge. The formative time lag depends on the ion drift velocity at the initial stage of discharge formation. This ion drift velocity becomes lager with higher helium atom concentration.

P‐61: New Driving Method for High Speed Addressing in AC PDP

AbstractA new high speed addressing method is proposed to reduce the addressing time below 1us per line in AC PDP. In this method, priming discharges are used to achieve a high speed addressing without adding an auxiliary electrode. The scan and sustain electrodes are divided into two groups even and odd lines and every even line is scanned first with priming discharges in the adjacent odd line electrodes and then every odd line is scanned through the selective erase addressing method. In the panel experiment, the address discharge time lag was reduced to one half of that of the conventional method when the new addressing method was used. Therefore, this addressing method is adequate to drive a high resolution PDP with a single scan method and it also can be used for high luminance and high picture quality by allocating the increased display time to sustain period or extra subfields.