Abstract
AbstractThe address discharge characteristics by the various scan‐low and common‐bias voltages are investigated based on measured address discharge time lags and Vt close‐curve analysis. The scan‐low voltages are changed with the same voltage difference between the X and Y electrodes during an address period, meaning that the voltage difference between the scan‐low voltage applied to the Y electrode and the common‐bias voltage applied to the X electrode remains constant even though each voltage level changes. As the voltage difference between the scan and address electrodes is increased during an address period, the address discharge time lag is shortened but a high background luminance is induced. It is found that the improved address discharge characteristics is caused by the effect of the higher external applied voltage during an address period than the accumulated wall charges during a reset period and the high background luminance can be prevented by applying an address‐bias voltage during a rising‐ramp period.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
