Adder Graph Research Articles

Difference Adder Graph Algorithm for Reducing LUT Size

The current study introduces an implementation of the Difference Adder Graph Algorithm (DAGA) using Verilog. DAGA, rooted in graph theory and adder circuits, aims to diminish Look Up Tables (LUTs) and power consumption in Field Programmable Gate Arrays (FPGAs). By reducing the number of LUTs required for a specific functionality, DAGA offers a promising alternative for digital circuit optimization. To evaluate its efficacy, the paper contrasts DAGA with the Multiple Constant Multiplication (MCM) method, which leverages Carry Save Adder (CSA) architecture and exploits signed-digit number representations to minimize LUT usage. Experimental findings reveal DAGA's superiority over MCM in both area and power utilization reduction. Implementation details and results indicate a remarkable 49.29% reduction in LUT count and a corresponding 41.8% decrease in power consumption for digital circuits. These outcomes underscore the effectiveness of DAGA in enhancing FPGA efficiency, highlighting its potential as a valuable tool for digital circuit designers seeking to optimize performance and power utilization.

Pelabelan Total Titik Ajaib Pada Graf Tangga

The labeling of a graph is a mapping that pairs the elements in the graph into positive integers. In this thesis, it discusses how the magic total point labeling algorithm on the ladder graph and the ladder graph and how the magic total point labeling on the ladder graph and the adder graph uses the magic square matrix modification using the durer method. Where the elements of the result of this magic square matrix modification will be used as point labels on the ladder graph and the ladder graph.

Using Transposition to Efficiently Solve Constant Matrix-Vector Multiplication and Sum of Product Problems

In this work, we present an approach to alleviate the potential benefit of adder graph algorithms by solving the transposed form of the problem and then transposing the solution. The key contribution is a systematic way to obtain the transposed realization with a minimum number of cascaded adders subject to the input realization. In this way, wide and low constant matrix multiplication problems, with sum of products as a special case, which are normally exceptionally time consuming to solve using adder graph algorithms, can be solved by first transposing the matrix and then transposing the solution. Examples show that while the relation between the adder depth of the solution to the transposed problem and the original problem is not straightforward, there are many cases where the reduction in adder cost will more than compensate for the potential increase in adder depth and result in implementations with reduced power consumption compared to using sub-expression sharing algorithms, which can both solve the original problem directly in reasonable time and guarantee a minimum adder depth.

A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard

For the next-generation video coding standard Versatile Video Coding (VVC), several new contributions have been proposed to improve the coding efficiency, especially in the transformation operations. This paper proposes a unified $32\times 32$ block-based transform architecture for the VVC standard that enables 2D Discrete Sine Transform-VII (DST-VII) and Discrete Cosine Transform-VIII (DCT-VIII) of all sizes. It mainly gives three contributions: 1) The N-Dimensional Reduced Adder Graph (RAG-n) algorithm is adopted to design the minimal adder-oriented computational units. 2) The storage of the asymmetric transform units can be realized in the dual-port SRAM-based transpose memory. 3) The pipelined 2D transformations of mixed block sizes are achieved with the throughput rate of 32 samples per cycle. The synthesis results indicate that this architecture can reduce area by up to 73.1% compared with other state-of-the-art works. Moreover, power saving ranging from 4.9% to 9.9% can be achieved. Regarding the transpose memory, at least 21.9% of the area can be saved by using SRAM.

Energy Efficient FIR Filter for Biomedical Application using FPGA

This research work proposes a low power Finite Impulse Response (FIR) digital filter system using Field Programmable Gate Array (FPGA) to filter biomedical signals. A major issue regarding such implementations is associated with computational complexity that may hinder its practical application. Several researches that aim to overcome this problem have been found by using various designs like booth multiplier, distributive arithmetic design, reduce adder graph (RAG), common sub-expression elimination method etc. This work has achieved the target of power line frequency of 50Hz noise cancellation. It is shown that the proposed design using RAG can give faster speed and require less hardware resources than that for the Direct Structure-I design. The performance of the proposed method is also compared with several existing research works to study its efficacy and it is shown that proposed design can achieve nearly 2% area delay product and 43% less power consumptions in implementation of an FIR low-pass filter. The designed filter is also tested on ECG waves as example of biomedical signal from samples of the MIT-BIH Arrhythmia database corrupted with power frequency noise. The entire system has been implemented on the ALTERA DE-II FPGA education board by synthesizing Verilog HDL using Quartus II tool.

Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs

Multiplication by a constant is a common operation for many signal, image, and video processing applications that are implemented in field-programmable gate arrays (FPGAs). Constant-coefficient multipliers (KCMs) are often implemented in the logic fabric using lookup tables (LUTs), reserving embedded hard multipliers for general-purpose multiplication. This paper describes a two-operand addition circuit from previous work and shows how it can be used to generate and add pre-computed partial products to implement KCMs. A novel method for pre-computing partial products for KCMs with a negative constant is also presented. These KCMs are then extended to have two to eight coefficients that may be selected by a control signal at runtime to implement time-multiplexed multiple-constant multiplication. Synthesis results show that proposed pipelined KCMs use 27.4% fewer LUTs on average and have a median LUT-delay product that is 12% lower than comparable LogiCORE IP KCMs. Proposed pipelined KCMs with two to eight selectable coefficients use 46% to 70% fewer LUTs than the best LogiCORE IP based alternative and most are faster than using a LogiCORE IP multiplier with a coefficient lookup function. They also outperform the state-of-the-art in the literature, using 22% to 57% fewer slices than the smallest pipelined adder graph (PAG) fusion designs and operate 7% to 30% faster than the fastest PAG fusion designs for the same operand size and number of selectable coefficients. For KCMs and KCMs with selectable coefficients of a given operand size, the placement and routing of LUTs remains the same for all positive and negative constant values, which is advantageous for runtime partial reconfiguration.

Reconfigurable Constant Multiplication for FPGAs

This paper introduces a new heuristic to generate pipelined run-time reconfigurable constant multipliers for field-programmable gate arrays (FPGAs). It produces results close to the optimum. It is based on an optimal algorithm which fuses already optimized pipelined constant multipliers generated by an existing heuristic called reduced pipelined adder graph (RPAG). Switching between different single or multiple constant outputs is realized by the insertion of multiplexers. The heuristic searches for a solution that results in minimal multiplexer overhead. Using the proposed heuristic reduces the run-time of the fusion process, which raises the usability and application domain of the proposed method of run-time reconfiguration. An extensive evaluation of the proposed method confirms a 9%–26% FPGA resource reduction on average compared to previous work. For reconfigurable multiple constant multiplication, resource savings of up to 75% can be shown compared to a standard generic lookup table based multiplier. Two low level optimizations are presented, which further reduce resource consumption and are included into an automatic VHDL code generation based on the FloPoCo library.

一种低面积低功耗RGB到YCbCr色彩空间转换电路实现方法

本文提出了一种低面积低功耗RGB与YCbCr色彩空间转换的电路实现方法。首先提出一种结合简化加法器图(Reduced Adder Graph, RAG)的公共子表达式消除(Common Subexpression Elimination, CSE)的电路实现，然后提出一个提高精度的补偿方法。最后采用TSMC 0.18um工艺对所提出的算法进行综合和布局布线。仿真和综合结果表明相比于传统的正则有符号数字(Canonic Signed Digit, CSD)编码系统，采用本文提出的结合CSE和RAG的RGB到YCbCr空间转换电路实现方法面积和功耗减小了20%，补偿算法提高了系统精度。 This paper presents a low-area and low-power circuit implementation of high-precision color space conversion from RGB to YCbCr. Firstly, an efficient circuit implementation combining com-mon-subexpression-elimination (CSE) with reduced-adder-graph (RAG) is presented. Secondly, a compensation method is proposed to enhance the precision. Finally, the synthesized results of a TSMC 0.18 um standard cell library are given. By using the proposed circuit implementation of color space conversion from RGB to YCbCr combining CSE and RAG without compensation, the results show that the area and power are reduced by about 20% than the traditional Canonic Signed Digital (CSD) method. With the compensation algorithm, the precision is much higher.

An improved constant coefficient multiplication algorithm based on cascaded adder graph

In many digital signal processing algorithms, e.g., digital filters, the multiplier coefficients are constant. Hence, it is possible to implement the multiplier using shifts, adders, and subtracters. In this work a new algorithm of constant coefficient multiplication with few adders and registers is proposed. This approach is based on cascaded adder graph. In this paper all cascaded adder graph structures for any integer can be derived, and the analytical method for the number of register and adder occupation is given. Through comparison of occupied resources, the optimal adder graph can be obtained. Finally, comparing with previous optimal algorithms, a design example for finite impulse response (FIR) filter confirms the validity and good engineering practicability of this algorithm.

MAG 알고리즘에 의한 힐버트 변환기의 하드웨어 복잡도 감소에 관한 연구

Abstract The Hilbert transform performs a role to transform band pass signals into low pass signals in wireless communication systems. The operation of Hilbert transform is based on a convolution process which is required adding and multiplying calculations. When the Hilbert transform is designed and hardware-implemented at gate level, the adding and multiplying operation requires a high power consumption and a occupation of wide area on a chip. So the results of adding and multiplying operation cause to degrade the performance of implemented system.In this paper, the new Hilbert transformer is proposed, which has a low hardware complexity by application of MAG(Minimum Adder Graph) algorithm. The proposed Hilbert transformer was simulated in ISE environment of Xilinx and showed the reduction of hardware complexity comparing with the number of gate in the conventional Hilbert transformer.Key Words : SOC, FPGA, Hilbert Transform, MAG algorithm 본 연구는 2010학년도 청운대학교 학술연구조성비에 의하여 수행되었음. * 교신저자 : 이영석(yslee@chungwoon.ac.kr)접수일 10년 10월 27일 수정일 (1차 10년 12월 15일, 2차 11년 01월 12일) 게재확정일 11년 01월 13일

An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth

It is well known that common subexpression elimination techniques minimize the two main cost metrics namely logic operators and logic depths in realizing finite impulse response (FIR) filters. Two classes of common subexpressions occur in the canonic signed digit representation of filter coefficients, called the horizontal and the vertical subexpressions. Previous works have not addressed the trade-offs in using these two types of subexpressions on the logic depth and the number of logic operators of coefficient multipliers. In this paper, we analyze the impact of the horizontal and the vertical common subexpression elimination techniques on reducing the logic depth and number of logic operators in FIR filters. Further, we present an algorithm to optimize the common subexpression elimination that produces FIR filters with fewer numbers of logic operators when compared with other common subexpression elimination algorithms in literature. The design examples show that the average reduction of logic operators achieved using our method over the weight-2 horizontal common subexpression elimination method which produced the best trade-off between logic operators and logic depth (contention resolution algorithm, CRA-2 [F. Xu, C.-H. Chang, C.-C. Jong, Contention resolution algorithm for common subexpression elimination in digital filter design, IEEE Trans. Circuit Syst. II 52(10) (2005) 695–700 (October)]) is 15%. This reduction of logic operators is achieved without any increase in the logic depth. When compared with the recently proposed multiple adder graph (MAG) algorithm [Jeong-Ho Han, In-Cheol Park, FIR filter synthesis considering multiple adder graphs for a coefficient, IEEE Trans. Comput.-Aid. Design Integ. Circuit Syst. 27(5) (2008) 958–962 (May)], the average reduction of logic operators obtained using our method is 5% and the reduction of logic depth is 25%.

Hardware-efficient realization of a real-time ultrasonic target detection system using IIR filters

In this study, we address the increased computational demands of a frequency-diverse ultrasonic target detection system by developing a zero-phase IIR (ZP-IIR) filter. Several ZP-IIR filter types including Chebyshev-I, Chebyshev- II, and Butterworth were analyzed for their detection performance. The 4th-order filters with 8-bit quantized coefficients are shown to improve the flaw-to-clutter ratio by approximately 10 dB. Furthermore, the reduced adder graph algorithm is used for a hardware realization of ZP-IIR filters that does not require any dedicated multipliers. A small number of coefficients inherent to IIR filters and their multiplierless implementation provide efficient architecture suitable for compact, real-time ultrasonic imaging devices.

Information Theoretic Approach to Complexity Reduction of FIR Filter Design

This paper presents a new paradigm of design methodology to reduce the complexity of application-specific finite-impulse response (FIR) digital filters. A new adder graph data structure called the multiroot binary partition graph (MBPG) is proposed for the formulation of the multiple constant multiplication problem of FIR filter design. The set of coefficients in any fixed point representation is partitioned into symbols so that common subexpression identification and elimination become congruent to information parsing for data compression. A minimum number of different pairs or groups of symbols and residues can be used to code a set of coefficients based on their probability and conditional probability of occurrence. This ingenious concept enables the notion of entropy to be applied as a quantitative measure to evaluate the coding density of different compositions of symbols towards a set of coefficients. The minimal vertex set MBPG synthesized by our proposed information theoretic approach results in direct correspondences between the vertices and adders, and edges and physical interconnections. Unlike the common subexpression elimination algorithms based on other graph data structures, the symbol-level information carried in each vertex and the graph isomorphism of MBPG promise further fine-grain optimization in a reduced search space. One such optimization that has been exploited in this paper is the shift-inclusive computation reordering to minimize the width of every two's complement adder to further reduce the implementation cost and the critical path delay of the filter. Experiment results show that the proposed algorithm can contribute up to 19.30% reductions in logic complexity and up to 61.03% reduction in critical path delay over other minimization methods.

FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient

To reduce the hardware complexity of finite-impulse response (FIR) digital filters, this paper proposes a new filter synthesis algorithm. Considering multiple adder graphs for a coefficient, the proposed algorithm selects an adder graph that can be maximally sharable with the remaining coefficients, whereas previous dependence-graph algorithms consider only one adder graph when implementing a coefficient. In addition, an addition reordering technique is proposed to derive multiple adder graphs from a seed adder graph generated by using previous dependence-graph algorithms. Experimental results show that the proposed algorithm reduces the hardware cost of FIR filters by 22% and 3.4%, on average, compared to the Hartley and -dimensional reduced adder graph hybrid algorithms, respectively.

Fast Discrete Fourier Transform Computations Using the Reduced Adder Graph Technique

It has recently been shown that the n-dimensional reduced adder graph (RAG-n) technique is beneficial for many DSP applications such as for FIR and IIR filters, where multipliers can be grouped in multiplier blocks. This paper highlights the importance of DFT and FFT as DSP objects and also explores how the RAG-n technique can be applied to these algorithms. This RAG-n DFT will be shown to be of low complexity and possess an attractively regular VLSI data flow when implemented with the Rader DFT algorithm or the Bluestein chirp-z algorithm. ASIC synthesis data are provided and demonstrate the low complexity and high speed of the design when compared to other alternatives.

Hamming weight pyramid – A new insight into canonical signed digit representation and its applications

Signed-power-of-two terms are widely used in design automation algorithms for digital filter synthesis and optimization, linear transformation and other multiple constant multiplication problems. In these applications, the computation efficiency or solution quality tends to degrade with the number of nonzero digits in the signed digit representation of the a priori fixed coefficients. This paper provides a new perspective to interpret the hamming weights of fixed-point coefficients represented in signed-power-of-two terms with minimal number of nonzero digits, called the minimal signed digit (MSD) representation. A new hamming weight pyramid (HWP) is proposed to succinctly compress the information about the distribution of the hamming weights of canonical signed digit (CSD) representation in a visually appealing manner for analysis and synthesis. CSD is a unique and popularly used subset of the general MSD representation. Many interesting properties of CSD are uncovered in this regularly structured HWP. These properties are exploited to develop a novel and elegant algorithm for the direct conversion of decimal number to CSD representation. We also show that the HWP can also be employed to overcome the limit imposed on the word length of the coefficients for the reduced adder graph (RAG) algorithm and filter coefficient synthesis.

Faster than the FFT: The chirp-z RAG-n Discrete Fast Fourier Transform

DFT and FFTs are important but resource intensive building blocks and have found many application in communication systems ranging from fast convolution to coding of OFDM signals. It has recently be shown that the n-Dimensional Reduced Adder Graph (RAG-n) technique is beneficially in many applications such as FIR or IIR filters, where multiplier can be grouped in multiplier blocks. This paper explores how the RAG-n technique can be applied to DFT algorithms. A RAG-n fast discrete Fourier transform will be shown to be of low latency and complexity and posses a VLSI attractive regular data flow when implemented with the Bluestein chirp-z algorithm. VHDL code synthesis results for Xilinx Virtex II FPGAs are provided and demonstrate the superior properties when compared with Xilinx FFT IP cores. Index Terms – Fast Fourier Transform, OFDM, FPGA, n-Dimensional Reduced Adder Graph

Modified reduced adder graph algorithm for multiplierless FIR filters

A modified reduced adder graph (MRAG) algorithm and its hybrid version are proposed for efficient digital filter implementation. Several improvements are made to exploit fully the efficient optimal part of the n-dimensional reduced adder graph (RAG-n) algorithm. Simulation results demonstrate that MRAG is capable of generating lower adder cost solutions.