Add-compare-select Unit Research Articles

Low Power Trellis Coded Modulation (TCM) Decoder by Using Modified Resource Sharing Method for IoT Enabler

This paper proposes a new pre-computation approach based on the auxiliary trellis of the TCM decoder's ACSU (add compare select unit). The suggested method is based on pre-computation of path metrics and resource sharing of the ACSU unit. The Viterbi decoder itself is a power-consuming module of the communication system that comprises the TMU (transition metric unit) and ACSU (add compare select unit). By applying the suggested method, the authors would be able to achieve low dynamic power. The TCM decoder designed accordingly shows better SER/ BER results in comparison to the existing techniques. The 4D 8 PSK TCM encoder and decoder were implemented as per the design specifications given by consultative committee for space data system (CCSDS) for satellite applications. The simulations results are observed on 100 Mbps data for 8PSK modulation and the ¾ code rate of the TCM encoder. The results based on the new method show improved power-speed ratio with improved SER and BER.

A Fast and Efficient Add-Compare-Select Structure Using Hybrid Logic Asynchronous Pipeline Design

Convolutional or trellis codes are today widely used in digital communication networks and multimedia broadcasting systems. TheViterbi decoder is commonly used for decoding trellis codes due to its excellent forward error correction performance. High-performance and low-power Viterbi decoders are in great demand in the communication industry. Despite several significant developments in decoder design and architecture in the past decade, the issue of latency and power dissipation still remains a challenge requiring further investigation and innovation. This paper proposes arobust deep-pipelined Add-Compare-Select (ACS) Unit, based on a hybrid logic asynchronous pipeline design method. The ACS operation forms the primary deadlock on the performance of the decoder hardware. With the proposed structure, the ACS units and hence Viterbi Decoder operate at a 323.3% higher throughput with 76.4% reduced latency and 86.6% reduced power consumption, when compared with QDI based realization of the ACS unit.

Power Consumption Optimization Technique in ACS for Space Time Trellis Code Viterbi Decoder

To provide fast digital communications systems, energy efficient, high-performance, low power is critical for decoding mobile receiver device. This paper proposes a low power optimization techniques in the Add Compare Select (ACS) unit for Space Time trellis codes (STTC) Viterbi decoder. STTC Viterbi decoder is used as a reference case. This paper discusses about how to lower the power in the ACS architecture, to optimize the Viterbi decoder STTC in reducing the total power consumption. Based on the results of design and analysis, power consumption Viterbi decoder modeling, low power system for STTC Viterbi decoder is proposed. Design and optimization of ACS unit in STTC Viterbi decoding is done using Verilog HDL language. Power analysis tools in the software Altera Quartus 2 is used for the synthesis of total system power consumption. Optimization strategy showed an increase of 83% power reduction compared to previous studies.

Low-power multi-standard Viterbi decoder for wireless communication applications

A Viterbi code is a type of the well-known error correcting code (ECC), which provides a robust error control methodology for wireless communication systems. It can efficiently reduce the bit error rate of the receiver and hence the reliability of the receiver is improved at data fidelity. This paper presents a novel low-power Viterbi decoder (VD) with a four-bit soft decision. To provide a multi-standard ECC processor, this study proposes a code rate 1/2 and 1/3 of VD used in software-defined radio systems for the hardware accelerator. Based on the proposed Viterbi decoding scheme, the survivor memory can be eliminated totally. This scheme achieves energy savings of approximately 50% of the total power dissipation and obtains a lower latency than that of most classical VDs. Furthermore, to avoid overflow occurrences in the add-compare-select unit (ACSU), a normalised mechanism is proposed, which only uses simple shifters and selection operations to reduce the design complexity. Finally, because it is designed with a 0.18 μm complementary metal-oxide-semiconductor technology, the proposed chip uses approximately 26.2 K gates, and its power consumption is approximately 11 mW at 73 MHz.

High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards

This work focuses on the VLSI design aspect of high- speed maximum a posteriori (MAP) probability decoders which are intrinsic building-blocks of parallel turbo decoders. For the logarithmic-Bahl-Cocke-Jelinek-Raviv (LBCJR) algorithm used in MAP decoders, we have presented an ungrouped backward recursion technique for the computation of backward state metrics. Unlike the conventional decoder architectures, MAP decoder based on this technique can be extensively pipelined and retimed to achieve higher clock frequency. Additionally, the state metric normalization technique employed in the design of an add-compare-select-unit (ACSU) has reduced critical path delay of our decoder architecture. We have designed and implemented turbo decoders with 8 and 64 parallel MAP decoders in 90 nm CMOS technology. VLSI implementation of an 8 × parallel turbo-decoder has achieved a maximum throughput of 439 Mbps with 0.11 nJ/bit/iteration energy-efficiency. Similarly, 64 × parallel turbo-decoder has achieved a maximum throughput of 3.3 Gbps with an energy-efficiency of 0.079 nJ/bit/iteration. These high-throughput decoders meet peak data-rates of 3GPP-LTE and LTE-Advanced standards.

A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks

Turbo codes have recently been considered for energy-constrained wireless communication applications, since they facilitate a low transmission energy consumption. However, in order to reduce the overall energy consumption, lookup table-log-BCJR (LUT-Log-BCJR) architectures having a low processing energy consumption are required. In this paper, we decompose the LUT-Log-BCJR architecture into its most fundamental add compare select (ACS) operations and perform them using a novel low-complexity ACS unit. We demonstrate that our architecture employs an order of magnitude fewer gates than the most recent LUT-Log-BCJR architectures, facilitating a 71% energy consumption reduction. Compared to state-of-the-art maximum logarithmic Bahl-Cocke-Jelinek-Raviv implementations, our approach facilitates a 10% reduction in the overall energy consumption at ranges above 58 m.

Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA

This paper presents a parameterized multi-standard adaptive radix-4 Viterbi decoder with high throughput and low complexity. The proposed Viterbi decoder supports constraint lengths ranging from 3-9, code rates in the range of 1/2-1/3, and arbitrary truncation lengths. We present a novel fabric of Add-Compare-Select Unit (ACSU) and methods of unsigned quantization and efficient normalization that shorten the critical path. The decoder achieves a low bit error ratio in multiple standards, such as GPRS, WiMax, LTE, CDMA, and 3G. The proposed decoder is implemented on Xilinx XC5VLX330 device and the frequency achieved is 181.7 MHz. The throughput of the proposed decoder can reach 363 Mbps, which is superior to the other current multi-standard Viterbi decoders or radix-4 Viterbi decoders on the FPGA platform. key words: multi-standard, radix-4, Viterbi decoder, FPGA

An Efficient 4-D 8PSK TCM Decoder Architecture

This paper presents an efficient architecture for a 4-D eight-phase-shift-keying trellis-coded-modulation (TCM) decoder. First, a low-complexity architecture for the transition metric unit is proposed based on substructure sharing. This scheme significantly reduces the required computation without degrading the performance. Then, a new hybrid T -algorithm for a Viterbi decoder is developed by applying a T-algorithm on both branch metrics (BMs) and path metrics (PMs). TCM encoders usually employ high-rate convolutional codes that yield many more transition paths per state than low-rate codes do. This makes it feasible to purge unnecessary additions by applying the T -algorithm on BMs. Applying the T-algorithm on BMs instead of PMs allows one to move the ?search-for-the-optimal? operation out of the add-compare-select-unit (ACSU) loop. Hence, the clock speed will not be affected. In addition, by combining the T-algorithm on BMs and the T-algorithm on PMs, the hybrid T -algorithm can reduce the computations required with the conventional T-algorithm on PMs by as much as 50%.

Error-Resilient Low-Power Viterbi Decoder Architectures

Three low-power Viterbi decoder (VD) architectures are presented in this paper. In the first, limited decision errors are introduced in the add-compare-select units (ACSUs) of a VD to reduce their critical path delays so that they can be operated at lower supply voltages without incurring timing errors. Power savings in this design can reach 58% and 44% with a 0.15 dB coding loss under reduced voltage operation and process variations, respectively, with adaptive supply voltage and adaptive body biasing applied to avoid timing errors. In the other two designs, we permit data-dependent timing errors to occur whenever a critical path in the ACSU is excited. Algorithmic noise-tolerance (ANT) is then applied to correct for these errors. Power reduction in these schemes is achieved by either overscaling the supply voltage [voltage overscaling (VOS)] or designing at the nominal process corner and supply voltage (average-case design). Two techniques are proposed to develop efficient estimators for error-correction and achieving increased robustness to timing based errors. The first is based on reduced-precision redundancy and the second on state clustering. The first can achieve up to 40% and 25% power savings under VOS and process variations with loss in coding gain of 1.1 and 1.2 dB, respectively, in a 130-nm CMOS process. The second can achieve up to 71% and 62% power savings under VOS and process variations, respectively, at a loss in coding gain of 0.8 and 0.6 dB, respectively. Under process variations, the designs achieve 16-33X improvement in bit error-rate (BER) performance at a signal-to-noise ratio (SNR) of 2 dB.

Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders

We present a systematic and efficient way of managing the path metric memory and simplifying its connection network to the add_compare_select unit (ACSU) for Viterbi decoder (VD) design. Using the derived equations for memory partition and add-compare-select (ACS) arrangement together with the extended in-place scheduling scheme proposed in this work, we can increase the memory bandwidth for conflict-free path metric accesses with hardwired interconnection between the path metric memory and ACSU. Compared with the existing work, the developed architecture possesses the following advantages: (1) Each partitioned memory bank can be treated as a local memory of a specific processing element, inside the ACSU, with hardwired interconnection, so that the interconnect complexity is reduced significantly. (2) The partitioned memory banks can be merged into only two pseudo-banks regardless of the number of adopted ACS processing elements. This not only greatly simplifies the design of address generation unit, but also makes smaller the physical size of required memory. (3) The implementation can be accomplished in a systematic way with regular and simple controlling circuitry. Experimental results demonstrate the effectiveness of the developed architecture and the benefit will be more apparent for convolutional codes with large memory order.

An Improved Pipelined MSB-First Add-Compare Select Unit Structure for Viterbi Decoders

Convolutional codes are widely used in many communication systems due to their excellent error-control performance. High-speed Viterbi decoders for convolutional codes are of great interest for high-data-rate applications. In this paper, an improved most-significant-bit (MSB) -first bit-level pipelined add-compare select (ACS) unit structure is proposed. The ACS unit is the main bottleneck on the decoding speed of a Viterbi decoder. By balancing the settling time of different paths in the ACS unit, the length of the critical path is reduced as close as possible to the iteration bound in the ACS unit. With the proposed retimed structure, it is possible to decrease the critical path of the ACS unit by 12% to 15% compared with the conventional MSB-first structures. This reduction in critical path can reduce the level of parallelism (and area) required for a very high-speed Viterbi decoder.

A Simplified Computational Kernel for Trellis-Based Decoding

A simplified branch metric and add-compare-select (ACS) unit is presented for use in trellis-based decoding architectures. The simplification is based on a complementary property of best feedforward and some systematic feedback encoders. As a result, one adder is saved in every other ACS unit. Furthermore, only half the branch metrics have to be calculated. It is shown that this simplification becomes especially beneficial for rate 1/2 convolutional codes. Consequently, area and power consumption will be reduced in a hardware implementation.

A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r=1/3 and the constraint length K=9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS placement and state metric routing topology is described for the 256 bit-serial ACS units, which achieves very high area efficiency. In the trace-back operation, a power efficient trace-back scheme, allowing higher memory read access rate than memory write in a time-multiplexing method, is implemented to reduce the number of iterations required to generate a decoded output. In addition, a low-power application-specific memory suitable for the function of survivor path memory has also been developed. The chip's core, implemented using 0.5-/spl mu/m CMOS technology, contains approximately 200 K transistors and occupies 2.46 mm by 4.17 mm area. This chip can achieve the decode rate of 20 Mb/s under 3.3 V and 2 Mb/s under 1.8 V. The measured power dissipation at 2 Mb/s under 1.8 V is only about 9.8 mW. The Viterbi decoder presented here can be applied to next generation wide-band code division multiple access (W-CDMA) systems.

A 140-Mb/s, 32-state, radix-4 Viterbi decoder

A 140-Mb/s, 32-state, radix-4, R=1/2, eight-level soft-decision Viterbi decoder has been designed and fabricated using 1.2- mu m double-metal CMOS. The architecture of the add-compare-select (ACS) array is based on a restructuring of the conventional radix-2 trellis into a radix-4 trellis. Radix-4 units, consisting of four 4-way ACS units, process two stages of the constituent radix-2 trellis per iteration. A four-way ACS circuit achieves an iteration delay 17% longer than comparable two-way ACS circuits, resulting in a factor of 1.7 increase in throughput. A ring-based ACS placement and state metric routing topology achieves an area efficiency comparable to radix-2 designs. In a process referred to as pretrace-back, one stage of lookahead is applied to the trace-back recursion, combining two radix-4 trace-back iterations into a single radix-16 iteration based on 4-b decisions. This allows implementation of trace-back using one compact, single-ported decision memory, organized as a cyclic buffer. A 7.30-mm*8.49-mm chip containing 146000 transistors achieves a radix-4 iteration rate of 70 MHz. >