ADC Topology Research Articles

A 12-bit Fine-Coarse Successive Approximation Stochastic Analog to Digital Converter

The surrounding world is composed of continuous time and amplitude analog signals, such as the sound signal picked by a microphone, the light entering a camera, the temperature measured by a thermocouple. In order to process these real world signals by computers, they have to be converted to digital signals. Rapid advances in media technology require high performance analog to digital converters ADCs. In this work, a 12-bit Successive Approximation Register SAR Stochastic Analog to Digital Converter ADC topology has been designed using complementary metal-oxide-semiconductor CMOS in a 0.35µm technology and a single supply voltage equal to 3.3V. In order to reduce the number conversion loops in a typical SAR ADC. 8-bits of the conversion are performed using the SAR ADC and the remainder is fed to the stochastic ADC. Taking the remainder from the SAR ADC allows the input signal of the stochastic ADC to fall within a limited range. The stochastic ADC performs 4-bit conversion using 512 parallel comparators. Since a large number of comparator is used, a simple single ended comparator has been proposed. The proposed comparator reduces the dissipated power by 38% compared to the conventional single ended comparators for each comparator. The gain of the proposed comparator has doubled compared to the conventional single ended comparator. Using this hybrid conversion also solves the problem of the limited input range for stochastic ADCs. Typical stochastic ADCs have an input range around 1mV, using a SAR ADC in the first stage increased the input voltage range to 3.3 V. The ADC has a sample rate of 50Ms/s. The proposed ADC achieves an SNDR equal to 71.2 dB. The DNL -0.44/+0.47 and INL -0.55/+0.59 LSB.

Advanced System Analysis and Survey on the GPS Receiver Front End

A fully integrated GPS receiver system can enable unique system capabilities by synthesizing both receiver front end and baseband on the same chip, leading to lower area overhead and higher integration. A survey on the GPS receiver system that focuses on front end design is presented in the paper. The first section discusses the various global navigation satellite system (GNSS), followed by the GPS working section. Afterwards, the paper discusses the previous works on the GPS receiver front end design. It provides a detailed survey and classification of various receiver architecture, including the LNA, mixer, filter, and ADC topologies. Besides, several image rejection techniques are presented for more than 50 GPS receivers. The various performance parameters of the GPS receiver front end in the literature are presented with the graphical view in the state-of-the-art discussion section. This literature survey provides the most extensive compilation to date of the various topologies, techniques and explains their implementation in the GPS receiver system. A new figure of merit that includes all the system parameters is proposed. The FOM can be an excellent reference to enhance the research work in the field of GPS receivers. In the end, the paper describes the possible research scope and challenges associated with the design of the GPS receiver front end.

Continuous-Time Acquisition of Biosignals Using a Charge-Based ADC Topology.

This paper investigates continuous-time (CT) signal acquisition as an activity-dependent and nonuniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by nonuniform quantisation to commonly recorded biological signal fragments allowing a compression ratio of 5 and 26 when applied to electrocardiogram and extracellular action potential signals, respectively. We describe several desirable properties of CT sampling, including bandwidth reduction, elimination/reduction of quantisation error, and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT analogue-to-digital converter that has been optimized for the acquisition of neural signals. This has been implemented in a commercially available 0.35 CMOS technology occupying a compact footprint of 0.12mm2. Silicon verified measurements demonstrate an 8-bit resolution and a 4kHz bandwidth with static power consumption of 3.75 W from a 1.5V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39pJ energy per conversion.

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

This brief presents a 10kS/s 14 bit 12.5 ENOB Successive Approximation Register Analog-to- Digital Converter for Cardiac Implantable Medical. For achieving power efficient operation, SAR ADC employ SAR control, a new power and noise efficient comparator topology, non- binary weighted capacitive DAC. The linearity of implemented SAR ADC is enhanced with the uniform geometry of non-binary weighted capacitive DAC.The proposed SAR ADC is implemented using 65nm CMOS technology. The latched comparator consumes a power of 2.4uW and it provides an ENOB of 12.6 at a supply voltage of 1V.The INL is between -2.7/+1.6 LSB and DNL is between -0.6/+1.4LSB. The FOM of ADC is 40fJ/conv. Step which is comparable with existing ADC topologies.

A Novel Stochastic ADC Topology with Wide Input Range

This paper describes a novel stochastic ADC topology with a wide input range. Stochastic ADC utilizes the randomness of process mismatch in comparators. Offset voltage which is Gaussian distributed represents the input range of stochastic ADCs. Stochastic ADCs have several limitations and drawbacks, such as limited input signal range and large number of required comparators to achieve high resolution. Some methods have been proposed to increase the input signal range at the expense of resolution. In this work we propose a novel stochastic ADC circuitry capable of increasing the input signal range without any sacrifice in the resolution. This new topology cycles the signal until it is within the offset voltage standard deviation. The Stochastic ADC is simulated using MATLAB SIMULINK.

A SAR ADC With a MOSCAP-DAC

The linearity of the vast majority of the ADC topologies is limited by the linearity of the circuit elements employed in their design, such as resistors and capacitors. This paper presents a charge-mode SAR ADC architecture that uses only highly non-linear metal-oxide-semiconductor capacitors (MOSCAPs) as the DAC capacitance elements. The non-linearity of the MOSCAPs is exploited to improve the tolerance of the ADC to comparator offset and noise. The architecture employs local voltage boosting and a new boost-and-bootstrap switch to allow operation with an over-rails input range. A 9 bit prototype is fabricated in a $0.13 \;\upmu\text{m}$ CMOS process and operates with a supply voltage of 0.6 V, handling a differential input range of $1.7\; \text{V}_\text{pp}$ . The prototype achieves an effective number of bits (ENOB) larger than 8.5 for a temperature range of $-40$ to 85°C, despite the strong dependency of MOSCAPs to temperature. Operating at 1 MSps, the prototype consumes $2.78 \;\upmu\text{W}$ , leading to a figure of merit (FoM) of 7.8 fJ/conversion-step.

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS

This paper presents a 28 nm CMOS 10 b SHA-less pipelined/SAR hybrid ADC, designed to enable a direct-sampling receiver system. To achieve low power at 5 GS/s, the ADC combines pipelined and SAR quantizers, powered at 1.8 V and 1 V, respectively. A 2.5 b 2-way time-interleaved 2.5 GS/s multiplying digital-to-analog converter (MDAC) is followed by an 8 b 8-way time-interleaved 625 MHz successive-approximation register (SAR). This architecture combines the benefits of both ADC topologies and allows significant power and complexity reduction. The high-speed 2.5 b MDAC front-end simplifies the complexity of time-interleaving (TI) and provides gain for attenuating the 8 b SAR non-idealities, when referred to the ADC input, relaxing its specifications and design. To further reduce power, the 2.5 b MDAC front-end is SHA-less, and an over-range calibration loop that allows operation at multi-GHz input is introduced. A calibration technique is also proposed to align the MDAC and SAR references, whose misalignment would otherwise produce integral non-linearity (INL) degradation. The ADC achieves ${-}$ 61.8 dB THD, 57.1 dB SNR for a 500 MHz input, while for a 2.35 GHz input it achieves ${-}$ 54.7 dB THD, 46.8 dB SNR (55.8 dB SNR excluding the integrated PLL contribution). The time-interleaving spur is ${ 70 dBc. The ADC consumes 150 mW and occupies less than 0.5 mm $^{2}$ .

High-Resolution CMOS Counter Type ADC Layout Design by using Transmission Gate Logic

In this paper, we propose counter type ADC for high-speed applications. Counter type ADCs are one of the most popular ADC topology used to implement moderate resolution converter due to their reasonably fast conversion time and simplicity.. Designed ADC has 8 input channels each of which has 0 – 2.6 V signal range. The resolution of ADC the converter is 8 bits. The amount of passing through a system from input to output ADCs can be increased by using its technique This is implemention on the circuit level with pass transistor circuit. The primary focus of this work design and implementation of a pass transistor based Analog-to-Digital converter. The proposed counter type ADC is composed of a 8-bit DAC design by using transmission gate logic, a comparator logic , 8 bit digital counter and “AND” gates to pass the clock signal by considering the chip area, operation speed, and circuit complexity.

VCO-based sigma delta modulator with PWM precoding

Presented is a new ADC topology based on an asynchronous PWM modulator followed by a VCO and a counter. The PWM modulator first encodes the analogue input into a binary waveform. Then, the VCO implements a multibit first-order noise shaping modulator, sampling and quantising the input signal encoded by the PWM modulator. With this architecture, the linearity of the whole converter is independent of the VCO linearity as the VCO is modulated by a two valued signal only. Proposed is a hardware implementation suitable for low power applications that does not require linear amplifiers.

A Low-Power Capacitive Charge Pump Based Pipelined ADC

A low-power pipelined ADC topology is presented which uses capacitive charge pumps, source-followers, and digital calibration to eliminate the need for power-hungry opamps to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves >10-bit linearity, and does not require an explicit common-mode-feedback circuit. The ADC was designed to operate at 50 MS/s in a 1.8 V, 0.18 ?m CMOS process, where measured results show the peak SNDR and SFDR of the ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits.

Low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs

A low-power parasitic-insensitive switched-capacitor (SC) integrator is proposed for ΔΣ ADCs. Compared to the conventional SC integrator, the new one achieves much lower power dissipation for the same sampling noise specification. A cancellation technique is used to reduce the nonlinearity of the integrator. An effective ΔΣ ADC topology is described which can incorporate the new integrator. Simulation shows that high linearity can be achieved by the new integrator, while consuming very low power.

Enhanced split-architecture delta–sigma ADCs

A split delta---sigma ADC topology is proposed, which provides enhanced noise shaping by cross-coupling the quantization errors of the two halves of the structure. Unlike the multi-stage noise shaping (MASH) architecture, the new structure is insensitive to mismatch errors, and it does not reduce the stability of the loops. Simulations confirm the effectiveness of the proposed scheme.

Enhanced split-architecture Δ-Σ ADC

A split Δ-Σ ADC topology is proposed which provides enhanced noise shaping by cross-coupling the quantisation errors of the two halves of the structure. Unlike the multi-stage noise shaping architecture, the new structure is insensitive to mismatch errors and it does not reduce the stability of the loops. Simulations confirm the effectiveness of the proposed scheme.